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112. 发明专利

JPH09330208A ADDING CIRCUIT 失效
公开(公告)号：JPH09330208A
公开(公告)日：1997-12-22
申请号：JP14891396
申请日：1996-06-11
申请人： HITACHI LTD
发明人： KAWASHIMA HIDEYUKI , NISHIOKA KIYOKAZU
IPC分类号： G06F7/50 , G06F7/508
摘要： PROBLEM TO BE SOLVED: To improve a throughput by providing a decision means which detects a break of a carry before addition and an end means which finishes the addition earlier if it is decided that an addition time is short since the carry is broken halfway. SOLUTION: This circuit is composed of an adding circuit 103 with output N105 which detects there is no carry from the 4th BIT to the 5th BIT of 8 BITs halfway in the addition of input registers A101 and B102 inputting two binary numbers, that is a break of carrier propagation and a control circuit 107 which outputs an addition end output 108 on the basis of a non-generation input N105 showing no carry from the 4th BIT to the 5th BIT. According to the state of the N105 showing there is the break of carry propagation, the control circuit 107 once receiving an addition request 106 moves to WAIT insertion and then to the end of the addition, that is two clocks when N105 is true, and moves to the end of the addition with one clock when false.

113. 发明专利

JPH09319728A ACCUMULATOR 失效
公开(公告)号：JPH09319728A
公开(公告)日：1997-12-12
申请号：JP14017396
申请日：1996-06-03
申请人： KOKUSAI ELECTRIC CO LTD
发明人： KONNO YOSHIYUKI
IPC分类号： G06F7/505 , G06F7/50 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To suppress power consumption of an accumulator by reducing the 1 to 0 or 0 to l change of a code bit and an extension code bit. SOLUTION: The accumulator is provided with a positive/negative judging circuit 11 judging the positive/negative of inputted numerical data to sort to positive or negative data (but an accumulator to which inputted data is not given is assigned with '0'). Two accumulators of an accumulator 12 accumulating sorted positive data (DATA>=0) and an accumulator 13 accumulating sorted negative data (DATA =0) and the accumulator 13 accumulates only negative data (DATA

115. 发明专利

JPH09244875A SEMICONDUCTOR ARITHMETIC CIRCUIT 失效
公开(公告)号：JPH09244875A
公开(公告)日：1997-09-19
申请号：JP8594896
申请日：1996-03-13
申请人： OMI TADAHIRO , SHIBATA SUNAO
发明人： OMI TADAHIRO , IMAI MAKOTO , KOTANI KOJI , SHIBATA SUNAO
IPC分类号： G06F7/509 , G06F7/49 , G06F7/501 , G06G7/14 , H01L27/10 , H03K19/20 , H03M1/00 , G06F7/50
摘要： PROBLEM TO BE SOLVED: To perform polynomial addition processing fast with small area by adding all the bits of data in binary notation which are inputted at the same time at a time and converting an analog signal which has linear relation with the addition result into a digital signal. SOLUTION: Input terminals 301-307 are coupled with floating electrodes 311-317 through capacitors to generate analog voltages to be supplied to the floating electrodes as an addition means of input bits. The floating electrodes are the gate electrodes of neuron MOS transistors and neuron MOS inverter circuits 321-327 which are different in threshold value are constituted. Then the inverter circuit 321 outputs 0 to an output terminal 331 when the batch addition result is >=1, the inverter circuit 322 outputs 0 to a terminal 322 when the batch addition result is >=2, and so on the inverter circuits 323-326 output 0; and the inverter circuit 327 outputs 0 to a terminal 337 when the batch addition result is >=7, and consequently 7 input bit data are added together at a time.

116. 发明专利

JPH09237179A MULTI-BIT ADDING CIRCUIT 失效
公开(公告)号：JPH09237179A
公开(公告)日：1997-09-09
申请号：JP7148196
申请日：1996-03-02
申请人： YAMAHA CORP
发明人： KOBAYASHI TAKAFUMI
IPC分类号： G06F7/50
摘要： PROBLEM TO BE SOLVED: To attain high speed in a carry operation in a multi-bit adding circuit. SOLUTION: The carry arithmetic part 1 of a first whole adder 10 is longitudinally connected to the carry arithmetic part 24 of the second whole adder 20. When addition inputs are adopted as A1 and B1, a carry input is C11, a carry outputs are CO1N and the inversion signals of A1 and C11 are respectively A1N and CI1N, the whole adder 10 transmits CO1N=A1N at the time of A1=B1≠CI1 and CO1N=CI1N in the other cases. CO1N corresponds to the inversion of the normal carry output CO1. When the addition inputs are adopted as A2 and B2, the carry input is CI2N=CO1N, the carry output is CO2 and the inversion signal of CI2N is CI2, the whole adder 20 transmits CO2=A2 at the time of A2=B2≠CI2 and CO2=CI2 in the other cases. Buffering is executed by a one-stage inverter at every carry bus.

118. 发明专利

JPH09167081A ADDING CIRCUIT 失效
公开(公告)号：JPH09167081A
公开(公告)日：1997-06-24
申请号：JP32755495
申请日：1995-12-15
申请人： TOSHIBA CORP
发明人： YAMAZAKI ITARU
IPC分类号： G06F7/50 , G06F7/506 , G06F7/507 , G06F7/508
摘要： PROBLEM TO BE SOLVED: To reduce unnecessary power consumption after operation by providing a means which cutting off a current flowing to a P-LOAD circuit (multi-input NOR circuit) mounted on a CLA(carry lock ahead) when all CSAs(carry select adder) finish operation. SOLUTION: A FLAG 7 inputs C0A and C1A outputted by CSA 1a, a carry from a low-order part, and a carry signal to a high-order signal and sets SFLAG to '1' according to a specific rule. Then FPR 9 which inputs this SFLAG propagates an operation end signal to high-order FPR 9 on condition that the operation end signal of low-order CSA is inputted. Similarly, each CSA performs operation and when the operation end signal reaches FPR 9 regarding the highest-order CSA and the operation of the highest-order CSA ends, it is outputted as an all-CSA operation end signal to respective CLAs. Each CLA once inputting the all-CSA operation end signal cuts off the current flowing in the circuit, so the input from each CSA stops.

119. 发明专利

JP2621480B2 失效
公开(公告)号：JP2621480B2
公开(公告)日：1997-06-18
申请号：JP14222689
申请日：1989-06-06
IPC分类号： G06F7/499 , G06F7/50 , G06F7/506 , G06F7/508 , G06F11/10 , G06F11/16 , G06F11/267

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