PROBLEM TO BE SOLVED: To attain high speed in a carry operation in a multi-bit adding circuit. SOLUTION: The carry arithmetic part 1 of a first whole adder 10 is longitudinally connected to the carry arithmetic part 24 of the second whole adder 20. When addition inputs are adopted as A1 and B1, a carry input is C11, a carry outputs are CO1N and the inversion signals of A1 and C11 are respectively A1N and CI1N, the whole adder 10 transmits CO1N=A1N at the time of A1=B1≠CI1 and CO1N=CI1N in the other cases. CO1N corresponds to the inversion of the normal carry output CO1. When the addition inputs are adopted as A2 and B2, the carry input is CI2N=CO1N, the carry output is CO2 and the inversion signal of CI2N is CI2, the whole adder 20 transmits CO2=A2 at the time of A2=B2≠CI2 and CO2=CI2 in the other cases. Buffering is executed by a one-stage inverter at every carry bus.