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111. 发明专利

JPS52123180A HIGH DIELECTRIC STRENGTH SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS52123180A
公开(公告)日：1977-10-17
申请号：JP3921976
申请日：1976-04-09
申请人： HITACHI LTD
发明人： MISAWA YUTAKA , NAGANO TAKAHIRO , YATSUNO KOUMEI
IPC分类号： H01L29/74
摘要： PURPOSE:To increase dielectric strengt and prevent cracking of wafers during producing by affixing a reinforcing plate to a wafer to reinforce the substrate, forming inner and outer annular grooves whose sum of depths is larger than the wafer thickness, and yet making the depth of the inner grooves depper than the depth of the outer grooves, in forming mesa type element.

112. 发明专利

JPS51123063A FABRICATION TECHNIQUE OF ELECTRODES FOR SEMICONDUCTOR DEVICES 失效
公开(公告)号：JPS51123063A
公开(公告)日：1976-10-27
申请号：JP4745975
申请日：1975-04-21
申请人： HITACHI LTD
发明人： KOIZUMI JIYUNICHI , NAGANO TAKAHIRO , YOKOTA TAKESHI , SANBE ISAMU , IKEDA HIROHIKO , YAGI HIDEYUKI
IPC分类号： H01L21/60 , H01L21/28
摘要： PURPOSE:To prevent the occurrence of inferior contact between the electrode and and the solder in fabricating the electrode composed of three metal layers; Al, Ni and Ag. This can be achieved by making the Ni-layer thicker than the Allayer by more than 4 times thereby preventing infiltration of Al atoms into the Ag-layer through the Ni-layer.

113. 发明专利

JPS5150678A 失效
公开(公告)号：JPS5150678A
公开(公告)日：1976-05-04
申请号：JP12517074
申请日：1974-10-30
申请人： HITACHI LTD
发明人： NAGANO TAKAHIRO
IPC分类号： H01L29/744 , H01L29/74

114. 发明专利

JP2000091586A ACTIVE MATRIX SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JP2000091586A
公开(公告)日：2000-03-31
申请号：JP25783698
申请日：1998-09-11
申请人： HITACHI LTD
发明人： WAKAGI MASATOSHI , NAGANO TAKAHIRO , MIKAMI YOSHIAKI , MIMURA AKIO , ANDO MASAHIKO
IPC分类号： H01L29/786 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a thin film transistor, which is excellent in light resistance, is low in off-state current, can restrain generation of a light leakage current and has stable characteristics, and also to provide a liquid crystal display device, which is low in power consumption, is high in luminance and is high in picture quality. SOLUTION: This device has a P-channel thin film transistor(TFT) 17, which has an insulating substrate 1, a semiconductor layer 3, a gate insulating layer 4, a gate electrode 5, an interlayer insulating layer 10, a drain electrode 12, a source electrode 13 and P-type regions 8, and an N-channel TFT 16 having N-type regions 6. Here, the TFT 17 has an offset region 9, which is adjacent to the electrode 5 and is provided on the side only of the positive electrode, which is positioned close to the electrode 5 on the side of the electrode 12 or the side of the electrode 13, and the TFT 16 has an offset region 7, which is adjacent to a gate electrode 5 and is provided close to the electrode 5 on the side only of the negative electrode which is positioned on the side of a drain electrode 12 or the side of a source electrode 13.

115. 发明专利

JPH0897297A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0897297A
公开(公告)日：1996-04-12
申请号：JP23182294
申请日：1994-09-27
申请人： HITACHI LTD
发明人： TAKASUGI KOICHI , MINAMI MASATAKA , YAMANAKA TOSHIAKI , MATSUZAKI NOZOMI , YAHATA HIDEJI , NAGANO TAKAHIRO
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE: To reduce the occupation area of a memory cell M so as to improve the integration of a semiconductor integrated circuit device in the semiconductor integrated circuit device having a memory cell M. CONSTITUTION: In a semiconductor integrated circuit device having a memory cell, a gate wiring 6 that is united respectively to a gate electrode 6A for a loading MISFET Qp2 and a gate electrode 6B for a driving MISFET Qd2 through a wiring 12A formed in a connecting hole 11A is electrically connected with a first impurity area 9A as a drain area for the loading MISFET Qp1 and a second impurity area 8A as an impurity area for one of the drain area for the loading MISFET Qd1 and the transfer MISFET Qt1.

116. 发明专利

JPH07307310A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07307310A
公开(公告)日：1995-11-21
申请号：JP9861094
申请日：1994-05-12
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , KOBAYASHI NOBUYOSHI , HONMA YOSHIO , YAHATA HIDEJI , MATSUZAKI NOZOMI , NAGANO TAKAHIRO
IPC分类号： H01L21/285 , H01L21/265 , H01L21/28 , H01L21/308 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78
摘要： PURPOSE:To stably form a metal silicide film on a gate electrode region or the like, by a method wherein, after a polycrystalline silicon deposition film is formed on the substrate surface containing a silicide film, heat treatment is performed, and unreacted polycrystalline silicon is selectively eliminated by wet-etching using etching solution whose main component is hydrazine. CONSTITUTION:A titanium silicide film 8 is formed on the surfaces of a gate electrode region 4 and a source/drain region 5. A deposition film 9 composed of polycrystalline silicon is formed on the whole surface of a substrate 1 containing the titanium silicide film 8. By performing heat treatment, reaction is generated between the polycrystalline silicon film 9 and the metal silicide film 8, which is subjected to phase inversion to low resistance composition. Further after the heat treatment, wet etching is performed by using etching solution whose main component is hydrazine, and unreacted polycrystalline silicon is eliminated. Hence only the polycrystalline silicon film 9 is completely eliminated without etching the titanium silicide film 8.

117. 发明专利

JPH0680830B2 失效
公开(公告)号：JPH0680830B2
公开(公告)日：1994-10-12
申请号：JP7263485
申请日：1985-04-08
申请人： HITACHI LTD
发明人： KOBAYASHI YUTAKA , NAGANO TAKAHIRO
IPC分类号： H01L21/76 , H01L21/764 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/784

118. 发明专利

JPH065745B2 失效
公开(公告)号：JPH065745B2
公开(公告)日：1994-01-19
申请号：JP17888986
申请日：1986-07-31
申请人： HITACHI LTD
发明人： YAZAWA YOSHIAKI , WATANABE TOKUO , HIRAISHI ATSUSHI , MINAMI MASATAKA , NAGANO TAKAHIRO
IPC分类号： H01L29/10 , H01L29/78 , H01L29/786 , H01L29/808 , H01L29/784

119. 发明专利

JPH04346471A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04346471A
公开(公告)日：1992-12-02
申请号：JP11989091
申请日：1991-05-24
申请人： HITACHI LTD
发明人： SAWAHATA YASUO , HIRAO MITSURU , NAGANO TAKAHIRO
IPC分类号： H01L21/8249 , H01L21/8244 , H01L27/06 , H01L27/11 , H01L29/78
摘要： PURPOSE:To lessen a logic section in junction capacity without not only lessening a memory cell in capacity but also inducing punch-through and enhancement in junction leakage current by a method wherein the width of the drain diffusion layer of a logic section is set smaller than that of a drain diffusion layer which serves as the memory node of a memory cell. CONSTITUTION:In a logic section, a polysilicon lead-out electrode 30 is led out onto an element isolating oxide film 3 so as to come into contact with a metal wiring layer 41 on the film 3, whereby a source and a drain diffusion layer are set in width just enough to come into contact, with the polysilicon lead-out, electrode 30, and Thus source and the drain can be lessened in area. After the electrode 30 is formed, ions are implanted controlling implantation energy, whereby the diffusion layers of a memory section and a logic section can be formed deep and shallow respectively. By this setup, a memory cell and a logic section can be set large and small in junction capacity respectively.

120. 发明专利

JPH02237151A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH02237151A
公开(公告)日：1990-09-19
申请号：JP5648989
申请日：1989-03-10
申请人： HITACHI LTD
发明人： SATO KAZUE , WATANABE TOKUO , YADORI SHOJI , MINAMI MASATAKA , NAGANO TAKAHIRO , SAWAHATA YASUO
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/10
摘要： PURPOSE:To reduce a soft error by alpha rays and by a negative power-supply noise from an input terminal by a method wherein a gate electrode of a CMOS transistor is formed of an electrode of one conductivity type and a driver MOS constituting a memory cell is formed as a MOS transistor of one conductivity type. CONSTITUTION:In the figure, a bipolar transistor is formed in A, an nMOS transistor is formed in B, a pMOS transistor is formed in C and a memory cell is formed in D. Electrodes 10a extracted from a base region 9 of the bipolar transistor and gate electrodes 10b of the MOS transistor are formed of a p-type electrode layer; a driver MOS of a memory cell is formed as a pMOS; in addition, an n type buried region is formed between an n-type region in which the memory cell has been formed and a p-type silicon substrate. Accordingly, the region where the memory cell has been formed is used as the n-type region; a junction is formed without forming a special region between the memory cell region and the substrate. Thereby, a soft error by alpha rays and a negative power-supply noise from an input terminal are cut off here; a malfunction of a memory is reduced; reliability can be enhanced.

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