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    • 102. 发明专利
    • GATE TURN OFF THYRISTOR
    • JPS5895865A
    • 1983-06-07
    • JP19284781
    • 1981-12-02
    • HITACHI LTD
    • YAO TSUTOMUNAGANO TAKAHIROOIKAWA SABUROU
    • H01L29/417H01L29/74H01L29/744
    • PURPOSE:To increase a current cutoff limit at which the turn OFF operation can be performed safely, by providing a rectangular shape of the main surfaces of a semiconductor pellet so that one side of the rectangle is longer than the opposite side, and aligning the longitudinal direction of each emitter belt shaped region with the longitudinal direction of the main surfaces. CONSTITUTION:The pellet 21 of the thyristor has a four layer structure pE, nB, pB, and nE between a pair of the main surfaces 211 and 212 which are located at opposing sides each other. The nE layer and pE layers are exposed in one main surface 211, and the pE layer is exposed in the other main surface 212. The nE layer comprises a plurality of long belt shaped regions 213 which are arranged so that their longitudinal direction is aligned with the longitudinal direction of the main surfaces. Each emitter belt shaped region 213 has a width of about 0.3mm. and a length of about 4.0mm.. Two emitter belts shaped regions are provided. A cathode electrode 22 is contacted with the two emitter belt shaped regions 213 at a low resistance. A gate electrode 23 is contacted with the surface of the pB layer surrounding the emitter belt shaped regions 213 at a low resistance. An anode electrode 24 is contacted with the surface of the opposite pE layer at a low resistance.
    • 103. 发明专利
    • GATE TURN OF THYRISTOR
    • JPS5834966A
    • 1983-03-01
    • JP13279581
    • 1981-08-26
    • HITACHI LTD
    • HARADA EIJISAKURADA SHIYUUROKUIKEDA HIROHIKONAGANO TAKAHIRO
    • H01L29/744H01L29/74
    • PURPOSE:To enable a good characteristic of each kind and a process of high power, by providing a fifth semiconductor layer beside four semiconductor layers as a thyristor and low-resistance-contacting the first main electrode to the first and fifth semiconductor layers. CONSTITUTION:A GTO unit 1 has a p type emitter layer 2, an n type base layer 3, p type base layer 4, an n type emitter layer 5 and an n type collector layer 6 which is buried in the p type emitter layer 2. The n type collector layer 6 is provided on a part whereon the n type emitter layer 5 is vertically projected on the lower main surface. To the p type emitter layer 2 and the n type collector layer 6, an anode electrode (first main electrode) 7 is low-resistance- contacted on the lower main surface (first main surface). On the upper main surface (second main surface), a gate electrode (control electrode) 8 is low- resistance-contacted to the p type base layer 4, and a cathode electrode (second main electrode) 9 is low-resistance-contacted to the n type emitter layer 5.
    • 105. 发明专利
    • Gate turn-off thyristor
    • 门关闭三通阀
    • JPS5778172A
    • 1982-05-15
    • JP15388880
    • 1980-11-04
    • Hitachi Ltd
    • NAGANO TAKAHIROYAO TSUTOMU
    • H01L29/744H01L29/08
    • H01L29/0839
    • PURPOSE:To obtain a thyristor having large maximum shut-off current by reducing the thickness of the center of a cathode-emitter layer forming a thyristor thinner than that at the periphery and forming a density peak higher than the impurity in the surface of a base layer adjacent to the cathode-emitter layer in the prescribed position in the base layer. CONSTITUTION:A semiconductor substrate 1 is formed of a P type anode-emitter layer 2, an N type base layer 3, a P type base layer 4 and N type cathode-emitter layer 5 made of center portion 51 and peripheral portion 52. The layer 2 is ohmically contacted with the anode electrode 6 formed on the lower main surface together with N type shortcircuit layers 31, 32 exposed on the lower main surface, and a control electrode 7 and a cathode electrode 8 are respectively formed at the layers 4, 5. In this structure, WnEC
    • 目的:通过将形成晶闸管的阴极 - 发射极层的中心的厚度减小到比周边薄的晶闸管的中心厚度,形成比基极表面的杂质更高的密度峰值,从而获得具有大的最大截止电流的晶闸管 在基层中的规定位置与阴极 - 发射极层相邻的层。 构成:半导体衬底1由中心部分51和周边部分52制成的P型阳极 - 发射极层2,N型基底层3,P型基极层4和N型阴极 - 发射极层5形成。 层2与形成在下主表面上的阳极电极6一起与暴露在下主表面上的N +型短路层31,32一起欧姆接触,并且控制电极7和阴极电极8分别形成在 在该结构中,设置WnEC
    • 106. 发明专利
    • Semiconductor device
    • 半导体器件
    • JPS5762562A
    • 1982-04-15
    • JP13757980
    • 1980-10-03
    • Hitachi Ltd
    • YAO TSUTOMUNAGANO TAKAHIRO
    • H01L29/41H01L23/48H01L29/417H01L29/74H01L29/744
    • H01L24/72H01L29/744H01L2924/01082H01L2924/1301H01L2924/00
    • PURPOSE:To obtain a GTO thyristor with the uniform operation of an operation region by forming an annular gate electrode plate partly in an opposed manner with a gate electrode and contacting it with a semiconductor substrate by the pressure from an external cathode electrode via an insulator. CONSTITUTION:An annular cathode electrode plate 101, a disc-shaped cathode electrode plate 102, a gate electrode plate 110 and a cathode electrode 6 of a GTO substrate 1 are contacted under pressure with each other. The plate 110 is bonded to an insulating ceramic ring 111, and is pressure contacted with the surface of the GTO substrae by the external pressure via the ring 111. A gate lead 112 is connnected to the plate 110. Since the thickness and the width of the plate 110 are sufficiently large and the resistance of the plate is low, the voltage drop of the direction along the gate electrode plate can be remarkably reduced, thereby equalizing the turn-OFF operation and a preferable turn-OFF characteristics can be obtained.
    • 目的:通过以与栅电极相对的方式部分地形成环形栅电极并通过绝缘体通过来自外部阴极的压力与半导体衬底接触来获得操作区域的均匀操作的GTO晶闸管。 构成:将GTO基板1的环状阴极电极板101,盘状阴极电极板102,栅电极板110和阴极电极6彼此压力接触。 板110结合到绝缘陶瓷环111,并通过环111通过外部压力与GTO基底的表面压力接触。栅极引线112连接到板110.由于厚度和宽度 板110足够大并且板的电阻低,可以显着地减小沿着栅电极板的方向的电压降,从而使关断操作均衡,并且可以获得优选的关断特性。
    • 107. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS56124238A
    • 1981-09-29
    • JP2661780
    • 1980-03-05
    • HITACHI LTD
    • YAO TSUTOMUNAGANO TAKAHIRO
    • H01L21/52H01L21/58H01L23/48H01L29/41H01L29/74
    • PURPOSE:To prevent the deformation caused by the creeping of the electrode film in a compressed type semiconductor device by a method wherein the inharmoniousness of the pressure welding strength between the electrode members to be pressure-welded for a wide area and the pressure welding strength between the electrode members to be pressure-welded on a narrow area is removed. CONSTITUTION:An n layer 211 is formed by performing a P-diffusion from one side and a pB layer 13 and a pB 11 layer are formed simultaneously by performing a Ga-diffusion from both sides using an n type Si substrate 1 as base. Then, an nE layer 14 and an n layer 214 are formed simultaneously by performing a B-diffusion from one side and subsequently, the concaved section to be used for a gate electrode 3 is formed by performing an etching. Then, an anode 5 is soldered using an Au-Sb alloy, an Al cathode 2, the gate electrode 3 and a film 22 are provided, and in between them an SiO2 film is covered. An electrode 2 and the film 22 are connected by placing a W buffer plate 4 on them, a Cu electrode is contacted to the W plate 4 and an electrode 5 and the pressure of approximately 1,000kg is applied. This pressure is applied not only to the cathode 2, but also to the metal film 22 having the same height and the pressure per unit are is decreased, thereby enabling to prevent the deformation caused by the creeping of the Al cathode 2 and to obtain an excellent electrical and thermal contact.