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91. 发明专利

JPS6251551B2 失效
公开(公告)号：JPS6251551B2
公开(公告)日：1987-10-30
申请号：JP16201681
申请日：1981-10-13
申请人： DAINIPPON SCREEN MFG
发明人： YAMADA MITSUHIKO
IPC分类号： A61B5/055 , A61B10/00 , G06F1/03 , G06F3/153 , G06T1/20 , G06T5/00 , H04N1/407 , H04N5/66 , H04N7/18

92. 发明专利

JPS62163140A LOGARITHM-TRUE VALUE CONVERTER 失效
公开(公告)号：JPS62163140A
公开(公告)日：1987-07-18
申请号：JP25711086
申请日：1986-10-30
申请人： IBM
发明人： JIYOON RABUAAN MITSUCHIERU , UIRIAMU BUUN PENEBEEKAA , JIERARUDO GOOTSUERU
IPC分类号： G06F7/556 , G06F1/03 , G06F7/52 , G06T3/00 , H03M7/40

93. 发明专利

JPS6158476A Control circuit of inverter 失效
标题翻译：逆变器控制电路
公开(公告)号：JPS6158476A
公开(公告)日：1986-03-25
申请号：JP17935684
申请日：1984-08-30
申请人： Mitsubishi Electric Corp
发明人： ITO TOMOTAKA
IPC分类号： G06F1/03 , H02M7/48
CPC分类号： G06F1/0342
摘要： PURPOSE: To improve the working efficiency of ROM minimizing a memory capacity for the ROM, by a method wherein desired conductive patterns are combined together, and wherein a control circuit for forming the AC control signal of sine wave PWM control is provided.
CONSTITUTION: Conductive patterns by electrical angle 30° are memorized in ROM6, and the data for output corresponding to the address indicated at 5 bits through up-down counter 9 are provided through the ROMf6. By a data selector (A)10, the data of 8 bit output of the ROM6 are respectively exchanged with electrical angle 30° for 8 bits, 7 bits, 6 bits, 5 bits, 4 bits, 3 bits, 2 bits, and 1 bit, and in later process, the conductive patterns by each 30° are formed. The conductive patterns divided into four by electrical angle 7.5° are selected by a clock synchronized with the desired electrical angle by a data selector (B) 11, and fundamental patterns 1, 2 for the conductive patterns by 6 every electrical angle 30° are provided for the output.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过将期望的导电图案组合在一起的方法来提高ROM的存储器容量的最小化的工作效率，并且其中提供了用于形成正弦波PWM控制的AC控制信号的控制电路。构成：电角度30度的导电图案被存储在ROM6中，并且通过ROMf6提供与通过升降计数器9以5比特指示的地址相对应的用于输出的数据。通过数据选择器（A）10，ROM6的8位输出的数据分别以电角度30度交换。对于8位，7位，6位，5位，4位，3位，2位和1位，在后续处理中，每个30度的导电图案。形成。导电图案分为四个，电角度为7.5度。由与数据选择器（B）11所期望的电角同步的时钟和导电图案的基本图案1,2选择，每个电角度为30度。被提供给输出。

94. 发明专利

JPS6129940A Arithmetic unit 失效
标题翻译：算术单位
公开(公告)号：JPS6129940A
公开(公告)日：1986-02-12
申请号：JP15154084
申请日：1984-07-21
申请人： Nec Corp
发明人： YAMADA IKUO
IPC分类号： G06F7/38 , G06F1/03 , G06F5/00 , G06F7/00 , G06F7/508 , G06F9/30 , G06F9/305 , H03M7/08
CPC分类号： G06F1/03
摘要： PURPOSE:To attain ease of pipeline control by executing a read of converting constant depending on an operation data with a fixed number at high speed without branching of a microinstruction so as to save the total processing cycle. CONSTITUTION:A constant memory address generating circuit 12 consists of a gate 14, AND gates 15, 16, and an OR gate 17. An address of a constant memory 8 is given by a K-field output 8-bit of a normal control memory CS7. A code output S of an operand 1-input register 1 is replaced into the least significant bit of the K-field 8-bit of a CS read register CSR5 depending on the value of an address change flag bit 3a of the constant memory output register 3. When the address change flag 3a is logical 0 and the K-field output of the CSR5 is K0- K7, the address of the constant memory 8 is similarly K0-K7. When the flag 3a is logical 1, the address is modified as K0-K6S by the code output S of the operand 1-input register 1.
摘要翻译：目的：为了节省整个处理周期，通过执行高速固定数目的操作数据读取转换常数，无需微指令分支，便于管道控制。构成：恒定存储器地址产生电路12由门14，与门15,16和或门17组成。恒定存储器8的地址由正常控制存储器的K场输出8位给出 CS7。根据常数存储器输出寄存器的地址改变标志位3a的值，将操作数1输入寄存器1的代码输出S替换为CS读寄存器CSR5的K字段8位的最低有效位当地址变化标志3a为逻辑0且CSR5的K场输出为K0〜K7时，恒定存储器8的地址同样为K0-K7。当标志3a为逻辑1时，通过操作数1输入寄存器1的代码输出S将地址修改为K0-K6S。

95. 发明专利

JPS60151746A ARITHMETIC CIRCUIT FOR INVERSE TRIGONOMETRIC FUNCTION 失效
公开(公告)号：JPS60151746A
公开(公告)日：1985-08-09
申请号：JP663984
申请日：1984-01-18
申请人： NIPPON ELECTRIC CO
发明人： SHIRASAWA SUSUMU
IPC分类号： G06F7/548 , F02B75/02 , G06F1/02 , G06F1/03
摘要： PURPOSE:To obtain an inverse trigonometric function arithmetic circuit which is capable of a high-speed operation with simple constitution, by using a means which copies an image after deciding a range of application within a cycle of the inverse trigonometric function which is read out of a ROM. CONSTITUTION:An input signal has the positive polarity in the first 1/4 cycle of a sine function supplied to an input terminal 1. At the same time, the primary function of the input signal is also positive. Therefore a primary derived function code discriminator 8 outputs a signal having the positive polarity. This needs no correction at all to the output of a ROM3, and a selector 15 has no changeover. The value outputted from the RAM3 to a point P2 of the input signal is given at a point P3. The polarity of the primary derived function is changed negative in the following 1/4-1/2 periods, and the ROM3 outputs the value of the point P3. In this case, however -pi is added to the P3 owing to the negative polarity and an image is copied to a point P4. While the point P4 is copied to a point P5 with changeover of the selector 15. Thus P5 shows the reversed sine value of the P1.

96. 发明专利

JPS6064204A DIGITAL RATIO METER 失效
公开(公告)号：JPS6064204A
公开(公告)日：1985-04-12
申请号：JP17222883
申请日：1983-09-20
申请人： NAMIKI YASUSHI
发明人： NAMIKI YASUSHI
IPC分类号： G01N33/49 , G01B11/28 , G06F1/03
摘要： PURPOSE:To simplify the operation and to make erroneous operation zero, by using an ROM, in which classification of a material on a scale board is inputted and a program is written beforehand so that percentage is obtained when the classification is inputted. CONSTITUTION:A glass tube 3 is mounted on a scale plate 1. Classification is inputted into an ROM12 by a switch 6 corresponding to a right end 4 of an opaque part and a switch 7 corresponding to a right end 5 of a transparent part. Meanwhile, in the ROM12, numerical values are written so that percetage is obtained with respect to the inputs made by the two switches. When the switch action is inputted, the digital value is directly displayed. Therefore the operation is simplified. Since the ROM is used, erroneous operation can be made zero.

97. 发明专利

JPS6039906A SINUSOIDAL WAVE GENERATING CIRCUIT 失效
公开(公告)号：JPS6039906A
公开(公告)日：1985-03-02
申请号：JP14800683
申请日：1983-08-15
申请人： SHIBAURA ENG WORKS LTD
发明人： UCHIYAMA SHIYUUICHI
IPC分类号： H03B28/00 , G06F1/03
摘要： PURPOSE:To generate a sinusoidal wave having a different phase by applying time division to access of an ROM so as to use only one ROM. CONSTITUTION:An address signal generator 1 generates an address signal in K- bit where the address value is circulated in a prescribed period and supplies the signal as a low-order side address signal of the ROM 2. The ROM 2 has address signal inputs in (K+1)-bit and its memory area is divided into two blocks corresponding to a two-phase sinusoidal wave to be generated. Two sinusoidal wave sample values having a different phase are stored in advance in each block. On the other hand, an LSB signal is fed to a timing pulse generating circuit 3, which generates a timing pulse TP dividing a time when the K-bit address signal shows an identical value into two based on the LSB signal. The TP is fed as the least significant bit address signal of the ROM 2, from which the sinusoidal wave sample value having a different phase is outputted in time division.

98. 发明专利

JPS58219849A Correcting circuit of error 失效
标题翻译：校正错误电路
公开(公告)号：JPS58219849A
公开(公告)日：1983-12-21
申请号：JP10280682
申请日：1982-06-15
申请人： Toshiba Corp
发明人： INAGAWA JIYUN , NANUN MASAHIDE , KOJIMA TADASHI
IPC分类号： H03M13/00 , G06F1/03 , G06F7/72 , G11B7/00 , G11B7/004 , G11B20/18 , H03M13/27
CPC分类号： G06F7/726 , G06F1/0307
摘要： PURPOSE:To simplify the constitution of the titled circuit, by executing multiplication of a galore body necessary for an error location calculator body by a linear shift register, and also executing division by converting its divisor into the reciprocal number and multiplying the converted reciprocal number by a dividend. CONSTITUTION:When divisor alpha data set in a shift register 53 is written in a conversion table stored in a converter 51 at the execution of alpha divided by alpha , reciprocal data alpha outputted from the converter 51 are supplied to a multiplier 54 as it is as multiplicand data and immediately multiplied with dividend data alpha supplied to the multiplier 54 through a shift register 52. When the alpha data are not included in the conversion table in the converter 51, Reciprocal data alpha are obtained by using the fact that alpha is made coincide with any of alpha in a process multiplying alpha with alpha several times. In said case, alpha is previously multiplied by the multiplicand alpha and these values are inputted to the multiplier 54 to find the required divided result from the multiplied result.
摘要翻译：目的：为了简化标题电路的结构，通过利用线性移位寄存器执行误差位置计算器主体所需的多余体的乘法，并且还通过将其除数转换为倒数来执行除法，并将转换的倒数乘以股息构成：当移位寄存器53中设定的除数α数据被写入存储在转换器51中的转换表中，执行α1除以α时，输出的倒数数据α<-j> 转换器51作为被乘数数据被提供给乘法器54，并且立即乘以通过移位寄存器52提供给乘法器54的除数数据α。当α数据不包括在转换表中时在转换器51中，通过使用将α与α<8k + 1>中的任一个与α与α相乘的过程来获得交互数据α< - （j + m）> >几次。在这种情况下，先前乘以被乘数α，并将这些值输入到乘法器54，以从相乘的结果中找到所需的分割结果。

99. 发明专利

JPS58501254A 失效
公开(公告)号：JPS58501254A
公开(公告)日：1983-07-28
申请号：JP50256882
申请日：1982-07-28
IPC分类号： H03B19/00 , G06F1/03 , H03B20060101 , H04L27/30 , H04M1/50 , H04Q1/45

100. 发明专利

JPS57187725A DIGITAL LOGARITHMIC CONVERTER 失效
公开(公告)号：JPS57187725A
公开(公告)日：1982-11-18
申请号：JP7167281
申请日：1981-05-13
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： ISHIZAWA YOSHINORI , ENDOU KENJIROU
IPC分类号： G06F1/02 , G06F1/03 , G06F7/556
摘要： PURPOSE:To reduce the circuit scale of a logarithmic converting means (e.g. memory) by performing logarithmic conversion after ranging which corresponds to the amount of digital input data. CONSTITUTION:Digital input data A consist of 16 bits; the high-order two bits are inputted to a priority encoder (PEN) 1, or detecting means, and all bits are inputted to a bit shift (BS) 2, or dividing means. The BS2 uses 2N as a division coefficient to perform division B=A/2N. The output B of the BS2 is supplied as address data to the 1st memory 3 composed of an ROM, or logarithmic converting means, etc., to perform logarithmic conversion like BL=logB. The output of a PEN1, on the other hand, is supplied as address data to the 2nd memory 4 to perform logarithmic conversion like C=log2N. Outputs BL and C of the memories 3 and 4 are added together by an adder 5 to obtain logarithmic conversion data on Y=BL+C=logA.

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