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91. 发明专利

JP2011146682A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011146682A
公开(公告)日：2011-07-28
申请号：JP2010235063
申请日：2010-10-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KITAGAWA MITSUHIKO
IPC分类号： H01L29/861 , H01L21/329 , H01L21/338 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/06 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/812
CPC分类号： H01L29/0634 , H01L27/0629 , H01L27/0814 , H01L29/063 , H01L29/0638 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/41 , H01L29/7803 , H01L29/7804 , H01L29/7805 , H01L29/7813 , H01L29/861 , H01L29/8611
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device securing a low threshold and higher voltage resistance, even if a Schottky electrode is not installed. SOLUTION: A cathode layer 1 of type N + is formed, in junction with a cathode electrode 100 and a drift layer 2 of type N in low impurity concentration is formed, in junction with the cathode layer 1. A plurality of trenches 4a, 4b are arranged on the upper surface of the drift layer 2, keeping a predetermined interval. Embedded electrodes 5a, 5b are respectively formed within the trenches 4a, 4b via insulating films 6a, 6b. An inter-trench region 7 is formed between the neighboring trenches. In addition, a universal contact layer 3, jointed with an anode electrode 200, is formed in junction with the inter-trench region 7, by alternately arranging a P + -layer 31 at a high impurity concentration and an N + -layer 32 at a high impurity concentration. Since the potential of the inter-trench region 7 under the thermal equilibrium condition is adjusted, the difference in the potential, from that of the drift layer 2 under the thermal equilibrium condition, is lower than built-in voltage that depends on the band gap of a semiconductor material used. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使没有安装肖特基电极，也提供确保低阈值和更高耐电压性的半导体器件。解决方案：形成与阴极电极100结合的类型为N + 的阴极层1，形成低杂质浓度的类型N的漂移层2，与阴极结合多个沟槽4a，4b布置在漂移层2的上表面上，保持预定的间隔。嵌入电极5a，5b分别经由绝缘膜6a，6b形成在沟槽4a，4b内。在相邻的沟槽之间形成沟槽间区域7。此外，通过交替地布置高杂质浓度的P + SP层 - 层31，与阳极电极200连接的通用接触层3形成为与沟槽间区域7结合，以及在高杂质浓度下的N + 层32。由于调节了热平衡条件下的沟槽间区域7的电位，所以在热平衡条件下，与漂移层2的电位差的电位差低于取决于带隙的内置电压的半导体材料。版权所有（C）2011，JPO＆INPIT

92. 发明专利

JP2010045335A Method for producing material layer in semiconductor body 有权
标题翻译：在半导体体内生产材料层的方法
公开(公告)号：JP2010045335A
公开(公告)日：2010-02-25
申请号：JP2009154216
申请日：2009-06-29
申请人： Infineon Technologies Austria Ag , インフィネオンテクノロジーズオーストリアアクチエンゲゼルシャフト
发明人： MAUDER ANTON , PFIRSCH FRANK , BERGER RUDOLF , SEDLMAIER STEFAN , LEHNERT WOLFGANG , FOERG RAIMUND , WILLMEROTH ARMIN , BAUMGARTL JOHANNES
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/78
CPC分类号： H01L21/8249 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/66734 , H01L29/7804 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a method for producing an extremely thin foreign material layer extending deep in a semiconductor body. SOLUTION: The method for producing a semiconductor element having the foreign material layer disposed in the semiconductor body includes the steps of: producing a trench having two opposite sidewalls and a bottom in the semiconductor body; producing the foreign material layer on a first one of the two sidewalls of the trench; and filling the trench by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于制造在半导体本体中深度延伸的极薄异物层的方法。解决方案：制造具有设置在半导体主体中的异物层的半导体元件的方法包括以下步骤：在半导体本体中制造具有两个相对的侧壁和底部的沟槽; 在沟槽的两个侧壁中的第一个侧壁上产生异物层; 以及通过将所述半导体材料外延地沉积到所述沟槽的两个侧壁和所述底部中的所述第二侧壁上来填充所述沟槽。版权所有（C）2010，JPO＆INPIT

93. 发明专利

JP2009088159A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009088159A
公开(公告)日：2009-04-23
申请号：JP2007254636
申请日：2007-09-28
申请人： Fuji Electric Device Technology Co Ltd , 富士電機デバイステクノロジー株式会社
发明人： IWAMURO NORIYUKI
IPC分类号： H01L29/78 , H01L27/04 , H01L27/06 , H01L29/06 , H01L29/861
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7808 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To simplify structure, to reduce on resistance, and to increase avalanche breakdown resistance, when using a super-junction semiconductor substrate. SOLUTION: The super-junction semiconductor substrate 1 is configured in such a manner that n-type semiconductor layers 21, 2 of a parallel pn structure are formed at a boundary region between an active area 24 and a peripheral breakdown-resistant structure area 25. A heavily doped region 22 is formed at the center between p-type semiconductor layers 4 sandwiching the n-type semiconductor layers 21, 2. A region where a source electrode 10 is in contact with a channel layer 7 is formed over the n-type semiconductor layers 21, 2. A portion where the heavily doped region 22 is in contact with the channel layer 7 functions as a diode. The breakdown voltage of the diode is set lower than that of the device. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：当使用超结半导体衬底时，为了简化结构，降低导通电阻和增加雪崩击穿电阻。解决方案：超结半导体衬底1以这样的方式配置，即在有源区24和外围抗击结构之间的边界区域形成并联pn结构的n型半导体层21 在夹在n型半导体层21,2的p型半导体层4之间的中心处形成重掺杂区22.在源极电极10与沟道层7接触的区域形成在 n型半导体层21,2。重掺杂区域22与沟道层7接触的部分用作二极管。二极管的击穿电压设置为低于器件的击穿电压。版权所有（C）2009，JPO＆INPIT

94. 发明专利

JP2008085189A Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：JP2008085189A
公开(公告)日：2008-04-10
申请号：JP2006265387
申请日：2006-09-28
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： NOGUCHI YASUNARI , ISHIDA HIROYASU , ONODERA SHIGEO
IPC分类号： H01L29/78 , H01L21/336 , H01L27/04 , H01L29/739
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/7804 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To ensure a high reverse breakdown voltage between source and drain without reducing an area of an operation region. SOLUTION: In the insulated gate semiconductor device, a channel region continuing to a transistor cell is also disposed in the lower part of a gate pad electrode. The channel region positioned on the lower part of the gate pad electrode is fixed with a source potential. In this way, even if the p+ type impurity region is not provided on the entire surface of the lower part of the gate pad electrode, a predetermined reverse breakdown voltage between source and drain can be ensured. Further, a protective diode 12d is formed on a conductive layer disposed on the outer periphery of the operation region. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了确保源极和漏极之间的高反向击穿电压，而不减少操作区域的面积。解决方案：在绝缘栅极半导体器件中，连续到晶体管单元的沟道区也设置在栅极焊盘电极的下部。位于栅极焊盘电极的下部的沟道区域固定有源极电位。以这种方式，即使在栅极焊盘电极的下部的整个表面上没有设置p +型杂质区域，也可以确保源极与漏极之间的规定的反向击穿电压。此外，在设置在操作区域的外周上的导电层上形成保护二极管12d。版权所有（C）2008，JPO＆INPIT

95. 发明专利

JP3982842B2 Semiconductor device 失效
公开(公告)号：JP3982842B2
公开(公告)日：2007-09-26
申请号：JP20436493
申请日：1993-08-18
申请人：株式会社ルネサステクノロジ
发明人：憲内田 , 功吉田 , 光造坂本 , 成雄大高 , 正義小林 , 春虎庄野 , 英樹角田 , 哲郎飯島
IPC分类号： H01L21/822 , H01L27/04 , H01L27/02 , H01L29/78 , H02H5/04 , H03K17/08 , H03K17/082
CPC分类号： H03K17/0822 , H01L27/0248 , H01L27/0251 , H01L27/0255 , H01L29/0696 , H01L29/7803 , H01L29/7804 , H02H5/044 , H03K2017/0806

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