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91. 发明专利

JP4621215B2 Modular i / o bank architecture 有权
公开(公告)号：JP4621215B2
公开(公告)日：2011-01-26
申请号：JP2007010029
申请日：2007-01-19
申请人：アルテラコーポレイションAltera Corporation
发明人：バーニーアリ , グエンカイ , サンキアカン , シャラグラサンジェイ , ティハックジェフリー
IPC分类号： H03K19/173 , H03K19/0175
CPC分类号： H03K19/17744

92. 发明专利

JP4551517B2 Circuit protection method and apparatus in the hot socket state 有权
公开(公告)号：JP4551517B2
公开(公告)日：2010-09-29
申请号：JP37611399
申请日：1999-11-30
申请人：アルテラコーポレイションAltera Corporation
发明人：メジアマニュエル
IPC分类号： G06F3/00 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/003
CPC分类号： H03K19/003

94. 发明专利

JP2010141901A Programmable high-speed input/output interface 有权
标题翻译：可编程高速输入/输出接口
公开(公告)号：JP2010141901A
公开(公告)日：2010-06-24
申请号：JP2010001545
申请日：2010-01-06
申请人： Altera Corp , アルテラコーポレイションAltera Corporation
发明人： WANG BONNIE I , SUNG CHIAKANG , HUANG JOSEPH , NGUYEN KHAI , PAN PHILIP
IPC分类号： G06F3/00 , H03K19/173 , G06F13/38 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/0175 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： PROBLEM TO BE SOLVED: To provide methods and apparatus which achieve both high-speed and low-speed, flexible inputs and outputs. SOLUTION: An input/output structure having a high-speed input, a high-speed output, a low- or moderate-speed input, and a low- or moderate-speed output is provided. One of the input and output circuits is selected and the other is deselected. The high-speed input and output circuits are comparatively simple, for example, they have only a clear signal for control line input and are able to interface with low-speed circuitry inside the core of an integrated circuit. The low- or moderate-speed input and output circuits are more flexible, for example, they have preset, enable and clear signals for control line input and are able to support JTAG boundary testing. These parallel high- and low-speed circuits are user selectable such that the input/output structure is optimized between speed and functionality depending on the requirements of the application. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供实现高速和低速，灵活的输入和输出的方法和设备。
解决方案：提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入/输出结构。选择其中一个输入和输出电路，另一个被取消选择。高速输入和输出电路比较简单，例如，它们只具有用于控制线路输入的清晰信号，并且能够与集成电路核心内的低速电路接口。低速或中速输入和输出电路更灵活，例如，它们具有用于控制线路输入的预设，使能和清除信号，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，以便根据应用的要求，在速度和功能之间优化输入/输出结构。版权所有（C）2010，JPO＆INPIT

96. 发明专利

JP4425897B2 Programmable logic device memory elements having a high power level 有权
公开(公告)号：JP4425897B2
公开(公告)日：2010-03-03
申请号：JP2006307333
申请日：2006-11-14
申请人：アルテラコーポレイションAltera Corporation
发明人：ティー．チャンマーク , リューリン−シー
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17784

97. 发明专利

JP4401470B2 How to ensure the ic package and migration route a compatible 有权
公开(公告)号：JP4401470B2
公开(公告)日：2010-01-20
申请号：JP9403699
申请日：1999-03-31
申请人：アルテラコーポレイションAltera Corporation
发明人：エム．シフレットエリック
IPC分类号： H01L23/12 , G05B19/05 , H01L23/498 , H01L23/50
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32225 , H01L2224/451 , H01L2224/4556 , H01L2224/45599 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/49171 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/01075 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , Y02P90/265 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals. The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout. Methods for dctermining an extended integrated circuit pin element layout starting from a base pin element layout are disclosed.

98. 发明专利

JP4362574B2 Static random access memory circuit 有权
公开(公告)号：JP4362574B2
公开(公告)日：2009-11-11
申请号：JP23335798
申请日：1998-08-19
申请人：アルテラコーポレイションAltera Corporation
发明人：リーアンディー
IPC分类号： G11C11/41 , G11C7/20
CPC分类号： G11C7/20

99. 发明专利

JP4300471B2 Arbitrary waveform synthesizer to use a free-running ring oscillator 有权
公开(公告)号：JP4300471B2
公开(公告)日：2009-07-22
申请号：JP2003581342
申请日：2002-03-25
申请人：アルテラコーポレイションAltera Corporation
发明人：カーリー，アダム，エル．
IPC分类号： H03K3/64 , H03K5/14 , B41J2/045 , B41J2/205 , B41J29/38 , G06F1/02 , G06F15/00 , G06K1/00 , H03B20060101 , H03B21/00 , H03K3/03 , H03K3/84 , H03K5/13 , H03K5/135 , H03K5/159 , H04N1/40 , H04N1/46
CPC分类号： G06F1/022 , G06F1/025 , H03K5/133 , H03K5/159 , H03L7/0814 , H03L7/16

100. 发明专利

JP4292182B2 Techniques to implement a hard-wired decoder in the differential input circuit 有权
公开(公告)号：JP4292182B2
公开(公告)日：2009-07-08
申请号：JP2005353080
申请日：2005-12-07
申请人：アルテラコーポレイションAltera Corporation
发明人：ビー・イー・ネ , ブーン・ジン・アン
IPC分类号： H03K19/0175 , H03K19/177
CPC分类号： H03K19/17744

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