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1. 发明专利

JPH1023012A TRANSMISSION TRAFFIC CONTROLLER 失效
公开(公告)号：JPH1023012A
公开(公告)日：1998-01-23
申请号：JP16884796
申请日：1996-06-28
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/825 , H04L12/851 , H04L12/911 , H04Q11/04 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To control plural quality classes inside the same VP and to enable transferring high quality data by giving the priority of a normal class> a forward direction resource managing cell(FRM cell)> a variable class at every virtual path(VP) within the range of max. velocity. SOLUTION: The transmission scheduler 35 of a transmission traffic controller 20 controls the max. velocity at every VP and also manages the velocity of variable class queue. That is, the transmission scheduler 35 controls a means for controlling max. velocity at every VP, a control parameter and the velocity of the variable class queue, controls the insertion of an FRM cell, monitors the reception of a backward direction RM cell(BRM cell) and controls the transmission velocity of a variable rate, according to the reception state of the RM cell and the contents of a congestion display bit. Then, in this case, the priority of the normal class> the FRM cell> the variable class is provided at every VP within the range of max. velocity.

2. 发明专利

JPH0525136B2 失效
公开(公告)号：JPH0525136B2
公开(公告)日：1993-04-12
申请号：JP19834683
申请日：1983-10-25
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： G06F12/00 , G06F13/18 , G06F15/16 , G06F15/177

3. 发明专利

JPH0642754B2 失效
公开(公告)号：JPH0642754B2
公开(公告)日：1994-06-01
申请号：JP19812986
申请日：1986-08-26
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： H04Q3/52 , H04Q11/04

4. 发明专利

JPS6354897A LEN CONVERTING SYSTEM FOR TIME DIVISION SPEECH PATH SWITCH 失效
公开(公告)号：JPS6354897A
公开(公告)日：1988-03-09
申请号：JP19812986
申请日：1986-08-26
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To deal with an LEN without considering the multiplexing rule of a time division speech path switch by an application software by obtaining a corresponding physical LEN or a logical LEN from a logical (subscriber line storing position number) LEN or a physical LEN inputted from an application program and executing an application such as a connection setting. CONSTITUTION:The address output line of a processor bus interface 111 is directly connected to the address line of a switch control memory 110 and the data reading line 114 of the switch control memory 110 is directly connected to the address line of a time slot memory 102. The mutual conversion of the logical LEN and the physical LEN is carried out by a conversion routine 301 and conversion tables 302, 303 on a main memory device 124. The conversion routine 301 is a control procedure for indexing the conversion tables 302 and 303 and carrying out the conversion of the LEN. In the conversion table 302, a main memory address corresponds to the logical LEN and the physical LEN is stored in the memory positions of the respective addresses.

5. 发明专利

JPH11252249A INTEGRATED EXCHANGE SYSTEM FOR VOICE DATA 失效
公开(公告)号：JPH11252249A
公开(公告)日：1999-09-17
申请号：JP5313598
申请日：1998-03-05
申请人： OKI ELECTRIC IND CO LTD
发明人： ISAKA MASAZUMI , MATSUNUMA KEIJI , SEKINE YOSHINORI
IPC分类号： H04M3/42 , H04M3/00 , H04M7/00 , H04Q3/58 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To provide an exchange wherein local area network-(LAN) and a private branch of exchange are integrated. SOLUTION: Telephone sets 11 of a private branch exchange, a trunk 12 of a telephone network relay line, data terminals 13, 14, and Internet protocol telephone sets 15, 16 are connected to an exchange 10 by transmission lines 101-106, and the data terminal 14 and the Internet protocol telephone set 15 are connected to the same line. A speech of each telephone set 11 is sent by mutual conversion between a voice signal and a signal processing protocol and a medium access control(MAC) frame by a subscriber circuit 17. The trunk 12 and the Internet protocol telephone sets 15, 16 send information in the form of the MAC frame. MAC circuits 181-186 that assemble/disassemble the MAC frame are connected to ports of a LAN switch 18 for switching the MAC frame and the switch 18 is connected to the transmission lines 101-106 via the MAC circuits 181-186.

6. 发明专利

JPS60201463A DMA DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS60201463A
公开(公告)日：1985-10-11
申请号：JP5741884
申请日：1984-03-27
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： G06F13/28
摘要： PURPOSE:To release a processor bus except the time of starting and completion of transfer between memories by making data transfer between memories through a direct memory access controlling circuit. CONSTITUTION:When a CPU transfers data from a memory MM1 to a memoru MM2 to the direct memory access controlling circuit for data transfer DMAC, start setting is made from the CPU to the DMAC through the processor bus P-BUS. When the condition for starting is made complete, the DMAC reads data from the MM1 through a data bus D-BUS, and similarly, writes data in the MM2. When the transfer of designated quantity of data is completed, the DMAC sends report of completion of memory transfer to the CPU through the P-BUS, and stands by. The CPU attains memory access and I/O control etc. exept when starting and completion.

7. 发明专利

JPH1155270A CELL EXCHANGE DEVICE 失效
公开(公告)号：JPH1155270A
公开(公告)日：1999-02-26
申请号：JP20430397
申请日：1997-07-30
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To change the number of storage lines and the combination of the speed of the storage lines by providing a buffer part which temporarily stoves respective inputted cells and a bus contention control part controlling read timing from the buffer part and timing contention and multiplexing and outputting the respective cells which are read by a bus. SOLUTION: An ATM exchange is provided with input control parts 11-15, a main switch part 16 and output control parts 17-20. The ATM exchange contention-controls the outputs of the cells inputted from the respective low speed lines to the multiplex bus 14 and multiplexes the cells from the respective lines on the bus 14 and therefore it can correspond to arbitrary line speed. Then, hardware constitution can be reduced by intensively giving a header required for switching in the switch part 16 by the header conversion part 15 prepared in common to the respective lines.

8. 发明专利

JPH05120125A DATA PROCESSOR 失效
公开(公告)号：JPH05120125A
公开(公告)日：1993-05-18
申请号：JP16537091
申请日：1991-07-05
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： G06F12/06
摘要： PURPOSE:To realize the data processor which can improve the processing throughput (average memory access speed) by succeeding conventional software and hardware to the utmost. CONSTITUTION:In addition to a main storage device 60, a high speed memory 12 for storing that which has higher access frequency in a program and data is provided. The high speed memory 12 is placed in the vicinity of a CPU 11 since a high speed is expected. In this case, an address space of the high speed memory 12 is formed as the same as a part of an address space of the main storage device 60. As for this overlap address space, the high speed memory 12 becomes effective. Therefore, this data processor is provided with a high speed memory access detecting circuit 14 for detecting an access of the overlap address space, and an access inhibiting circuit 23 for inhibiting an access of the main storage device 60 at the time of its detection.

9. 发明专利

JPH03204742A MEMORY CONTROL CIRCUIT 失效
公开(公告)号：JPH03204742A
公开(公告)日：1991-09-06
申请号：JP44090
申请日：1990-01-08
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： G06F12/00
摘要： PURPOSE:To constitute the circuit so that a memory access of a bus master can be received by setting a memory clock of a memory control circuit independently from a clock of a CPU. CONSTITUTION:A clock generating means generates a clock being independent from a clock of a bus master. From a processor bus 7, an address signal and an address effective signal of a memory 4 are inputted, a memory access is detected, an address of the memory 4 is selected, a line selecting signal and a row selecting signal of the memory 4 are outputted, and a first time limit corresponding to a period in which the line and the row signals are outputted is started. Subsequently, from the bus 7, a data effective signal of a prescribed unit and a read/write discriminating signal are inputted, a selected address of the memory 4 is set to a read/write state, and a second time limit corresponding to a read/write period of the bus master is started. At the time point when a first time limit is ended and a second time limit is started, an access response signal is outputted to the processor bus 7, and by the end of a second time limit, each signal is released. In such a way, a memory access of the bus master can be received.

10. 发明专利

JPS6091473A MEMORY MULTI-ACCESS SYSTEM 失效
公开(公告)号：JPS6091473A
公开(公告)日：1985-05-22
申请号：JP19834683
申请日：1983-10-25
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNUMA KEIJI
IPC分类号： G06F12/00 , G06F13/18 , G06F15/16 , G06F15/177
摘要： PURPOSE:To increase the response speed to an access and to improve the operation efficiency of a memory multi-access system by selecting a clock for control of common memory which is used as a basic for synchronization and multiplexing in response to the speed of a common memory. CONSTITUTION:Accesses are given to a common memory 12 from processors 10-0-10-n via bus switch control parts 11-0-11-n containing a buffer function and an interface function. In this case, a CM control part 18 selects a common memory access request which has the highest priority and is not selected yet among those access requests to a common memory 12 generated by the processors 10-0-10-n for each clock cycle of the control clock of the memory 12. At the same time, the part 18 permits an access to the memory 12 only for one clock cycle of the parts 11-0-11-n corresponding to the processor that produced a common memory access request selected in a cycle immediately preceding by one clock cycle.

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