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1. 发明专利

JP2004165605A Semiconductor unit, semiconductor module, and memory system 有权
公开(公告)号：JP2004165605A
公开(公告)日：2004-06-10
申请号：JP2003103681
申请日：2003-04-08
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , エルピーダメモリ株式会社 , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： SENBA SEIJI , ANPO HISASHI , ONO TAKAO , HOSOKAWA KOJI , NISHIO YOJI , NAKAMURA ATSUSHI , SATO TOMOHIKO
IPC分类号： G06F12/00 , G06F13/16 , G11C5/00 , G11C11/24 , H01L23/12 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor unit capable of a high-speed operation, by contracting the wiring length of a branch wiring existent in its signal wiring. SOLUTION: A semiconductor unit 104, constituting a memory device comprises a memory chip 120 and a package board 121, has three wiring layers. The wirings of power-supply surfaces 118 (a VDD surface), 119 (a GND surface) are formed in the package board 121, and the wiring of an intra-package DQ bus 114 is formed in an intermediate wiring layer, interposed between both the power-supply surfaces 118, 119. The memory device 120 has two DQ pins 112 inside the one intra-package DQ bus 114. The intra-package DQ bus 114 and a signal-terminal pad 115 of the memory chip 120 are connected through the intermediary of a via. The via, whereby the intra-package DQ bus 114 and the signal-terminal pad are connected, constitutes a branch wiring, as viewed from the two DQ pins. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2011004038A Semiconductor lsi and semiconductor device 审中-公开
标题翻译：半导体LSI和半导体器件
公开(公告)号：JP2011004038A
公开(公告)日：2011-01-06
申请号：JP2009144111
申请日：2009-06-17
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NANBA AKIHIRO , NAKAMURA SATOSHI , NISHIO YOJI
IPC分类号： H04L25/02
CPC分类号： H03K19/003
摘要： PROBLEM TO BE SOLVED: To provide a technique which reduces noise or jitters caused by wiring length resonance even in a semiconductor device or a signal transmission system the data rate of which is variable.SOLUTION: In the signal transmission system which performs signal transmission through signal wiring 4-1 to 3 between a memory 1 and a memory controller 2 mounted on a printed circuit board 3, if the noise or the jitters is increased by wiring length resonance at a specified data rate for the memory 1 and the memory controller 2, the system has registers 6-1, 6-2 which hold information of the data rate. The signal transmission system has namely, a control system to change a relation of the registers 6-1, 6-2 which save the data rate of the wiring length resonance, the clock frequency, and wiring length, so as to control the data rate or transmission delay time so as to avoid resonance.
摘要翻译：要解决的问题：提供一种降低由布线长度谐振引起的噪声或抖动的技术，即使在数据速率可变的半导体器件或信号传输系统中也是如此。解决方案：在通过信号执行信号传输的信号传输系统中在存储器1和安装在印刷电路板3上的存储器控制器2之间的布线4-1至3，如果通过针对存储器1和存储器控制器2的指定数据速率的布线长度谐振增加噪声或抖动，该系统具有保存数据速率信息的寄存器6-1,6-2。信号传输系统具有改变保存布线长度谐振的数据速率，时钟频率和布线长度的寄存器6-1,6-2的关系的控制系统，以便控制数据速率或传输延迟时间，以避免共振。

3. 发明专利

JP2010027137A Semiconductor device and information processing system 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：JP2010027137A
公开(公告)日：2010-02-04
申请号：JP2008186707
申请日：2008-07-18
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , SAITO TATSUYA , NISHIO YOJI , HIROSE YUKITOSHI
IPC分类号： G11C11/4076 , G11C11/401 , G11C11/406
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and an information processing system, which reduces a power source noise.
SOLUTION: A DRAM memory includes 8 memory banks MBK0-MBK7, for instance. A control is made to refresh each of the memory banks MBK0-MBK7 with different time difference. Concretely, the time difference tRF_1 between the MBK0 and MBK1 in an initial stage is made large, the time difference is stepwise reduced up to the time difference tRF_4 between the MBK3 and MBK4 in an intermediate stage, and then the difference is stepwise increased up to the time difference tRF_7 between the MBK6 and MBK7 in a final stage. Thus, a power source current waveform in refresh operation becomes sinusoidal, thereby the power source noise can be reduced in accordance with the reduction in harmonic components.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供减少电源噪声的半导体器件和信息处理系统。解决方案：DRAM存储器包括例如8个存储体MBK0-MBK7。进行控制以用不同的时间差刷新每个存储体MBK0-MBK7。具体地说，在初始阶段MBK0与MBK1之间的时差tRF_1变大，在中间阶段将时差逐步减小到MBK3与MBK4之间的时间差tRF_4，然后逐渐增加到在最后阶段MBK6和MBK7之间的时差tRF_7。因此，刷新动作中的电源电流波形变为正弦波，从而能够根据谐波分量的降低来降低电源噪声。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009303245A Semiconductor device with digital interface 有权
标题翻译：具有数字接口的半导体器件
公开(公告)号：JP2009303245A
公开(公告)日：2009-12-24
申请号：JP2009216805
申请日：2009-09-18
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI , SHOJI KAZUYOSHI
IPC分类号： H04L7/02 , G06F3/00 , H03K5/00 , H03K5/135 , H04L25/03
摘要： PROBLEM TO BE SOLVED: To provide an LSI, for reducing jitter depending on a data pattern by using a receiver of an interface, which is capable of automatically adjusting setting of a delay amount for reduction. SOLUTION: In a semiconductor device, since a previous state of data pattern dependent jitter is predictable, a state of data received by a receiver is held and timing to capture input data is adjusted from the held state and from input data. As an adjustment mechanism inside the receiver for determining a delay amount depending on a mounting form, pulse data at intervals of one cycle and pulse data at intervals of two cycles are transmitted/received from a driver as a test pattern. An automatic adjustment mechanism for determining a delay amount optimal for a system from a rising and falling time difference of pulses having different pulse widths, is provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于通过使用能够自动调整用于减小的延迟量的设置的接口的接收器来减少根据数据模式的抖动的LSI。解决方案：在半导体器件中，由于数据模式相关抖动的先前状态是可预测的，因此保持由接收器接收的数据的状态，并且从保持状态和输入数据调整捕获输入数据的定时。作为用于根据安装形式确定延迟量的接收器内的调节机构，以一个周期的间隔的脉冲数据和以两个周期的间隔的脉冲数据作为测试图案从驾驶员发送/接收。提供了一种用于从具有不同脉冲宽度的脉冲的上升和下降时间差确定系统最优的延迟量的自动调整机构。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009164478A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009164478A
公开(公告)日：2009-07-23
申请号：JP2008002536
申请日：2008-01-09
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SUZUKI HIDEKAZU , OSAKA HIDEKI , UEMATSU YUTAKA , NISHIO YOJI
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L25/18 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01055 , H01L2924/15311 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To reduce power supply noise, etc. by increasing a value of electrostatic capacity of a power supply line at low cost without increasing a layout area of a semiconductor chip. SOLUTION: A semiconductor device 1 includes a chip-on-chip structure wherein semiconductor chips 4-12 are respectively laminated on a principal surface of an interposer 2. The semiconductor chips 4-12 are supplied with power-supply voltage via through vias 4b-12b and 4c-12c. The semiconductor chips 5-12 include through vias 5e-12e and 5f-12f connected to the through vias 5b-12b and 5c-12c, respectively. The through vias 5e and 6e, the through vias 7e and 8e, the through vias 9e and 10e and the through vias 11e and 12e are connected via a bump 14, an further the through vias 5f and 6f, the through vias 7f and 8f, the through vias 9f and 10f and the through vias 11f and 12f are connected via a bump 15, respectively. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过以较低的成本增加电源线的静电容量的值来降低电源噪声等，而不增加半导体芯片的布局面积。解决方案：半导体器件1包括片上芯片结构，其中半导体芯片4-12分别层压在插入件2的主表面上。半导体芯片4-12被提供有电源电压通孔通孔4b-12b和4c-12c。半导体芯片5-12分别包括连接到通孔5b-12b和5c-12c的通孔5e-12e和5f-12f。通孔5e和6e，通孔7e和8e，通孔9e和10e以及通孔11e和12e经由凸块14，通孔5f和6f以及通孔7f和8f连接，通孔9f和10f以及通孔11f和12f分别经由凸块15连接。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008258312A Semiconductor device, and interconnection component thereof 有权
标题翻译：半导体器件及其互连组件
公开(公告)号：JP2008258312A
公开(公告)日：2008-10-23
申请号：JP2007097380
申请日：2007-04-03
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NISHIO YOJI , SUZUKI HIDEKAZU
IPC分类号： H01L25/00
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/111 , H05K2201/0175 , H05K2201/0179 , H05K2201/09763 , H05K2201/10515 , H05K2201/10522 , H05K2201/10734 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology for increasing a mounting density while reducing noise in a semiconductor device.
SOLUTION: An LSI 102 mounted on a printed wiring board 101 has a BGA ball 105b for grounding and a BGA ball 105a for power supply, both of which are for receiving power from the printed wiring board 101. The BGA ball 105b for grounding and the BGA ball 105a for power supply are adjacent to each other. The printed wiring board 101 is mounted with a decoupling capacitor 103, which has a terminal 113 and a terminal 114. The BGA ball 105b for grounding and the terminal 113 are connected by a metal electrode flat plate 110, while the BGA ball 105a for power supply and the terminal 114 are connected by a metal electrode flat plate 111. Between the metal electrode flat plate 110 and the metal electrode flat plate 111, a dielectric film 112 having a thickness of 1 μm or less is interposed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于提高安装密度同时降低半导体器件中的噪声的技术。解决方案：安装在印刷电路板101上的LSI102具有用于接地的BGA球105b和用于从印刷线路板101接收电力的用于电源的BGA球105a。用于BGA球105b的BGA球105b用于接地和用于供电的BGA球105a彼此相邻。印刷线路板101安装有具有端子113和端子114的去耦电容器103.用于接地的BGA球105b和端子113通过金属电极平板110连接，而用于功率的BGA球105a 电源和端子114通过金属电极平板111连接。在金属电极平板110和金属电极平板111之间插入厚度为1μm以下的电介质膜112。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2008124732A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008124732A
公开(公告)日：2008-05-29
申请号：JP2006305622
申请日：2006-11-10
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SUZUKI HIDEKAZU , UEMATSU YUTAKA , OSAKA HIDEKI , SAITO TATSUYA , NISHIO YOJI , ITAYA SATORU
IPC分类号： H03K19/0175 , H03K19/003
摘要： PROBLEM TO BE SOLVED: To achieve extension of a noise margin in a semiconductor device.
SOLUTION: For example, a line 3a for transmitting a data signal DQ from an external terminal 10 toward one end (point B) of a receiver 6 and a line 3b for transmitting a reference voltage Vref from an external terminal 11 toward the other end (point D) of the receiver 6 are provided and are disposed so as to be electromagnetically coupled. Furthermore, a transmission line 4 having a characteristic impedance lower than that of the line 3b is provided between the external terminal 11 and one end (point C) of the line 3b. When the data signal DQ is transmitted in the line 3a, a backward crosstalk signal having the same polarity as the data signal is induced in the line 3b and is reflected at the point C with the opposite polarity, and this reflection signal is transmitted to the point D. Thus, an input potential difference of the receiver 6 is increased.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：实现半导体器件中噪声容限的扩展。解决方案：例如，用于将数据信号DQ从外部端子10向接收器6的一端（B点）发送的线3a和用于从外部端子11向基准电压Vref发送参考电压Vref的线3b 提供了接收器6的另一端（点D）并且被设置成电磁耦合。此外，在外部端子11和线3b的一端（点C）之间设置具有低于线3b特性阻抗的传输线4。当在线路3a中发送数据信号DQ时，在线路3b中感应出具有与数据信号相同极性的反向串扰信号，并以相反极性的C点反射，并将该反射信号发送到点D.因此，接收机6的输入电位差增大。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2008004853A Laminated semiconductor device, and module 审中-公开
标题翻译：层压半导体器件和模块
公开(公告)号：JP2008004853A
公开(公告)日：2008-01-10
申请号：JP2006174687
申请日：2006-06-26
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , SHOJI KAZUYOSHI , NISHIO YOJI , HIROSE YUKITOSHI , ITAYA SATORU
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145 , H01L2924/01055
摘要： PROBLEM TO BE SOLVED: To provide a technique contributing to an improvement of power supply efficiency to an upper layer semiconductor chip, reduction of power supply noise interference between upper and lower semiconductor chips, attainment of the low power supply noise, and high speed operation of a laminated semiconductor device (CoC).
SOLUTION: In the laminated semiconductor device, an interposer 11 is inserted between laminated semiconductor chips 1, 1. The interposer 11 has a feature of its being a high dielectric material such as ceramic whereby the intereposer enjoys both of an electric charge storage function by high capacitance, and of small size filter function. Use of a ceramic interposer having such functions ensures an improvement of power supply capability to the upper layer semiconductor chip noise interference reduction between the upper and lower semiconductor chips.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种有助于提高上层半导体芯片的电源效率的技术，降低上下半导体芯片之间的电源噪声干扰，实现低电源噪声和高层叠半导体器件（CoC）的快速操作。解决方案：在层叠半导体器件中，插入层11插入层叠的半导体芯片1,1之间。插入件11具有诸如陶瓷之类的高介电材料的特征，由此，插入器既具有电荷存储功能由高电容和小尺寸滤波功能。使用具有这种功能的陶瓷插入件确保了上层半导体芯片对上半导体芯片和下半导体芯片之间的噪声干扰降低的电力供应能力的改善。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2006173409A Module 有权
标题翻译： MODULE
公开(公告)号：JP2006173409A
公开(公告)日：2006-06-29
申请号：JP2004365004
申请日：2004-12-16
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI
IPC分类号： H01L21/8238 , G06F3/00 , G11C11/401 , H01L27/092
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a module wiring method by which both auto-noise and propagation noise can be effectively reduced. SOLUTION: In a memory module, a plurality of memories 2 are mounted on a module substrate 1, Vref-Vss impedance near the memories 2 is coupled with Vss by a decoupling capacitor 5 and Vref planes 4 to reduce impedance, the Vref plane 4 is individually provided for each memory 2, and the Vref planes 4 are connected by high-impedance wiring or high-impedance chip components 3-1, 3-2. COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2007065765A Designing method for semiconductor device, designing support system, program and semiconductor package 有权
标题翻译：半导体器件设计方案，设计支持系统，程序和半导体封装
公开(公告)号：JP2007065765A
公开(公告)日：2007-03-15
申请号：JP2005247935
申请日：2005-08-29
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KATAGIRI MITSUAKI , NAKAMURA SATOSHI , SUGA TAKU , ISA SATOSHI , NISHIO YOJI , SENBA SEIJI , HIROSE YUKITOSHI
IPC分类号： G06F17/50 , H01L21/82 , H01L23/12 , H05K3/00
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To propose a new design method for reducing a designing period. SOLUTION: In this designing method, an impedance model of an adjustment target system is calculated from adjustment target system information (step S101), a model of the whole semiconductor system is derived from a previously created chip model or a chip model created on the basis of design data and the impedance model, and a voltage fluctuation spectrum (an adjustment target value) is calculated (step S102). It is compared with a restriction value (a voltage fluctuation spectrum) in a frequency area (step S103). When a frequency portion regarded as questionable is present, a part to be performed with a design change is specified from a corresponding frequency portion, and the design change to be performed (a design guideline) is determined (step S104). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提出一种减少设计周期的新设计方法。解决方案：在该设计方法中，根据调整目标系统信息计算调整目标系统的阻抗模型（步骤S101），从先前创建的芯片模型或创建的芯片模型导出整个半导体系统的模型根据设计数据和阻抗模型，计算电压波动谱（调整对象值）（步骤S102）。将其与频率区域中的限制值（电压波动谱）进行比较（步骤S103）。当存在被认为有问题的频率部分时，从对应的频率部分指定要进行设计变更的部分，并且确定要执行的设计变更（设计准则）（步骤S104）。版权所有（C）2007，JPO＆INPIT

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