专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2004221459A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004221459A
公开(公告)日：2004-08-05
申请号：JP2003009490
申请日：2003-01-17
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KITAMURA EIJI , YAMADA SATORU , KATO YOSHIKI , SAINO KANTA , SAITO MASAYOSHI , IIJIMA SHINPEI , OYU SHIZUNORI
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28247
摘要： PROBLEM TO BE SOLVED: To reduce the gate resistance of a semiconductor device by reducing contact resistance between a tungsten film and a polysilicon layer, and at the same time, suppressing the occurrence of depletion in the gate electrode of the device.
SOLUTION: At the time of manufacturing the semiconductor device in which the gate electrode is constituted in a three-layered poly-metal gate structure composed of the tungsten film (W) 23, a tungsten nitride film (WN) 24, and the polysilicon layer (PolySi) 22; the side face of the gate electrode is nitrided at a nitriding temperature of 700-950°C in an ammonia atmosphere before the side face is selectively oxidized after the gate electrode is formed.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：通过降低钨膜和多晶硅层之间的接触电阻，同时抑制器件的栅极电极的耗尽，从而降低半导体器件的栅极电阻。解决方案：在制造其中栅电极由钨膜（W）23，氮化钨膜（WN）24和氮化钨膜（W））组成的三层多金属栅极结构中的半导体器件制造时，多晶硅层（PolySi）22; 在形成栅极电极之后，在侧面被选择性地氧化之前，在氨气氛中，在700-950℃的氮化温度下氮化栅电极的侧面。版权所有（C）2004，JPO＆NCIPI

2. 发明专利

JP2013098214A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013098214A
公开(公告)日：2013-05-20
申请号：JP2011237030
申请日：2011-10-28
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66477 , H01L21/76895 , H01L21/823443 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L21/823878 , H01L27/10814 , H01L27/10891 , H01L27/10894
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of connecting electrodes with each other without disconnection, which are separately arranged by being formed in separate processes; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises: burying a compensation film between a first electrode formed on a principal surface of a semiconductor substrate via a first insulation film and a second electrode formed on the principal surface of the semiconductor substrate via a second insulation film; and forming wiring above the first electrode and the second electrode, touching a top face of the first electrode and a top face of the second electrode and reaching from the top face of the first electrode via a top face of the compensation film to the top face of the second electrode.
摘要翻译：要解决的问题：提供一种能够在不断开的情况下彼此连接电极的半导体器件，其通过在分开的工艺中形成而分开布置; 并提供半导体器件的制造方法。解决方案：半导体器件制造方法包括：经由第一绝缘膜在半导体衬底的主表面上形成的第一电极和形成在半导体衬底的主表面上的第二电极之间的补偿膜经由第二绝缘膜绝缘膜; 以及在所述第一电极和所述第二电极之上形成布线，接触所述第一电极的顶面和所述第二电极的顶面，并且经由所述补偿膜的顶面从所述第一电极的顶面到达所述顶面的第二电极。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2013026494A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013026494A
公开(公告)日：2013-02-04
申请号：JP2011160791
申请日：2011-07-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10852 , H01L27/10873 , H01L27/10885
摘要： PROBLEM TO BE SOLVED: To selectively remove an aluminum oxide film provided between a plurality of first wirings in a second region while preventing an oxidant from entering a gate insulation film in a first region.SOLUTION: An insulation film is so formed as to cover a side wall of a first laminate in a first region and to cover a plurality of first wirings in a second region, and the insulation film is used as a mask to perform first ion implantation into the first region. A second insulation film whose main subject is aluminium oxide is so formed as to cover the side wall of the first laminate in the first region and to fill space between the plurality of first wirings in the second region. After that, the second insulation film is used as a mask to perform second ion implantation in the first region. The second insulation film is selectively removed from the first insulation film.
摘要翻译：要解决的问题：为了选择性地除去设置在第二区域中的多个第一布线之间的氧化铝膜，同时防止氧化剂进入第一区域中的栅极绝缘膜。解决方案：绝缘膜形成为覆盖第一区域中的第一层压体的侧壁并且覆盖第二区域中的多个第一布线，并且将绝缘膜用作掩模以执行第一离子注入第一区域。其主要对象是氧化铝的第二绝缘膜形成为覆盖第一区域中的第一层压体的侧壁并填充第二区域中的多个第一布线之间的空间。之后，将第二绝缘膜用作掩模，以在第一区域中进行第二离子注入。从第一绝缘膜选择性地去除第二绝缘膜。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2008181936A Method for detecting junction position 审中-公开
标题翻译：检测连接位置的方法
公开(公告)号：JP2008181936A
公开(公告)日：2008-08-07
申请号：JP2007012491
申请日：2007-01-23
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/66 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for detecting the position of a metallurgical PN junction in the semiconductor substrate of a micro semiconductor device by predicting and controlling the device characteristics of a transistor precisely and performing failure analysis of a specific part.
SOLUTION: The method for detecting the junction position of a P-type impurity region doped with P-type impurities and an N-type impurity region doped with N-type impurities on a semiconductor substrate comprises a step for exposing the cross-section becoming an observation object from the semiconductor substrate, a step for cleaning the cross-section, a step for depositing a silicide on the cross-section, and a step for detecting the junction interface by observing the grain size of the silicide.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过预测和控制晶体管的器件特性并执行特定部分的故障分析来检测微型半导体器件的半导体衬底中的冶金PN结的位置的方法。解决方案：用于检测掺杂有P型杂质的P型杂质区和在半导体衬底上掺杂有N型杂质的N型杂质区的结位置的方法包括：从半导体衬底变成观察对象的部分，用于清洁横截面的步骤，在横截面上沉积硅化物的步骤，以及通过观察硅化物的晶粒尺寸来检测接合界面的步骤。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007194486A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007194486A
公开(公告)日：2007-08-02
申请号：JP2006012716
申请日：2006-01-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To manufacture an anti-fuse element by utilizing an already existent manufacturing process as it is, without altering an already existent manufacturing process of a MOS transistor. SOLUTION: In a semiconductor device, the anti-fuse element 103 has a predetermined region 11b corresponding to a channel region 11a of a cell transistor 101 and having the same conductivity type as the channel region 11a, an insulating film 12b corresponding to the gate insulating film 12a of the cell transistor 101, an electrode 13b corresponding to the gate electrode 13a of the cell transistor 101 and having the same conductivity type as the gate electrode 13a, and diffusion regions 14b, 14b' corresponding to source/drain regions 14a, 14a' of the cell transistor 101 and having the same conductivity as the source/drain regions 14a, 14a'. Hereupon, the anti-fuse element 103 is formed by utilizing the manufacturing process of the cell transistor 101 as it is. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过利用已经存在的制造工艺原样制造抗熔丝元件，而不改变MOS晶体管的已有的制造工艺。解决方案：在半导体器件中，反熔丝元件103具有对应于单元晶体管101的沟道区域11a并且具有与沟道区域11a相同的导电类型的预定区域11b，对应于单元晶体管101的栅极绝缘膜12a，与单元晶体管101的栅电极13a对应并具有与栅电极13a相同的导电类型的电极13b以及与源/漏区对应的扩散区14b，14b' 并且具有与源极/漏极区域14a，14a'相同的导电性。因此，通过利用单元晶体管101的制造工艺来形成反熔丝元件103。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006196689A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006196689A
公开(公告)日：2006-07-27
申请号：JP2005006678
申请日：2005-01-13
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L29/423 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/78
CPC分类号： H01L21/82345 , H01L21/823842 , H01L27/10894
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device, capable of lowering both interface resistances of an N-type poly-metal gate electrode and a P-type poly-metal gate electrode.
SOLUTION: The manufacturing method for the semiconductor device has a process, in which a silicon film is formed on a semiconductor substrate 101, the process in which the ions of P-type impurities are implanted in the region P of the silicon film and the ions of N-type impurities in the region N in this order, and the process in which a silicide film 106 and a metal film are formed on the silicon film in this order. The manufacturing method further has a process in which the silicon film; the silicide film 106 and the metal film are patterned and the P-type poly-metal gate electrode is formed in a region P and the N-type poly-metal gate electrode in a region N; P-type impurities are activated by a first heat treatment before the ion implantation of N-type impurities, after the ion implantation of P-type impurities; and the silicon film in the region P is formed in a polysilicon film 103P; the N-type impurities are activated by a second heat treatment, after the ion implantation of the N-type impurities, and the silicon film in the region N is formed in the polysilicon film 103n. A gas contained in the silicide film 106 is removed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够降低N型多金属栅电极和P型多金属栅电极的界面电阻的半导体器件的制造方法。解决方案：半导体器件的制造方法具有其中在半导体衬底101上形成硅膜的工艺，其中P型杂质的离子注入到硅膜的区域P中的工艺以及N区中的N型杂质的离子，以及在硅膜上依次形成硅化物膜106和金属膜的工序。该制造方法还具有硅膜; 图案化硅化物膜106和金属膜，并且在区域N中形成P型多金属栅电极和N型多金属栅电极; 在P型杂质的离子注入之后，在离子注入N型杂质之前通过第一次热处理激活P型杂质; 并且区域P中的硅膜形成在多晶硅膜103P中; 在N型杂质的离子注入之后，通过第二次热处理来激活N型杂质，并且在多晶硅膜103n中形成区域N中的硅膜。除去包含在硅化物膜106中的气体。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2013093451A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2013093451A
公开(公告)日：2013-05-16
申请号：JP2011234894
申请日：2011-10-26
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent invasion of an oxidant from a second insulation film into a gate insulation film in a first region; and selectively remove, with respect to a first insulation film, the second insulation film provided among a plurality of first wirings in a second region.SOLUTION: A semiconductor device manufacturing method comprises: forming a first laminate in a first region of a substrate and forming a plurality of first wirings in a second region of the substrate; performing ion implantation of a first impurity into a principal surface of the first region by using a first insulation film as a mask; forming a second insulation film so as to cover side walls of the first laminate and fill between the plurality of first wirings; performing ion implantation of a second impurity into the principal surface of the first region by using the second insulation film as a mask; selectively removing the second insulation film with respect to the first insulation film by first etching; and performing a heat treatment on the substrate.
摘要翻译：要解决的问题：为了防止第一区域中的氧化剂从第二绝缘膜侵入到栅极绝缘膜中; 并且相对于第一绝缘膜选择性地移除在第二区域中的多个第一配线之间提供的第二绝缘膜。解决方案：半导体器件制造方法包括：在衬底的第一区域中形成第一层压体并在衬底的第二区域中形成多个第一布线; 通过使用第一绝缘膜作为掩模，将第一杂质离子注入第一区域的主表面; 形成第二绝缘膜以覆盖第一层压体的侧壁并填充在多个第一布线之间; 通过使用第二绝缘膜作为掩模，将第二杂质离子注入第一区域的主表面; 通过第一蚀刻相对于第一绝缘膜选择性地去除第二绝缘膜; 并对该基板进行热处理。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2013051250A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013051250A
公开(公告)日：2013-03-14
申请号：JP2011187225
申请日：2011-08-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/336 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/51 , H01L21/28044 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To reduce Schottky resistance caused by contact with a polycrystalline silicon film.SOLUTION: A semiconductor device comprises a transistor. The transistor has: a first gate insulating film covering a part of a surface in a first active region and made of a first insulation material having a dielectric constant higher than that of silicon dioxide; a first metal gate electrode formed on the first gate insulating film and made of a first metal material; and a first polycrystalline silicon film of a p-type conductivity type formed on the first metal gate electrode.
摘要翻译：要解决的问题：减少与多晶硅膜接触引起的肖特基电阻。解决方案：半导体器件包括晶体管。晶体管具有覆盖第一有源区的表面的一部分并由介电常数高于二氧化硅的第一绝缘材料制成的第一栅极绝缘膜; 形成在所述第一栅极绝缘膜上并由第一金属材料制成的第一金属栅电极; 以及形成在第一金属栅电极上的p型导电类型的第一多晶硅膜。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2008181935A Method for detecting junction position 审中-公开
标题翻译：检测连接位置的方法
公开(公告)号：JP2008181935A
公开(公告)日：2008-08-07
申请号：JP2007012490
申请日：2007-01-23
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L21/66 , H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for detecting the position of a PN junction in the semiconductor substrate of a micro semiconductor device by predicting and controlling the device characteristics of a transistor precisely and performing defect analysis of a specific part.
SOLUTION: The method for detecting the junction position of a P-type impurity region and an N-type impurity region on a semiconductor substrate comprises a step for making a sample by exposing the cross-section of an observation object, a step for cleaning the cross-section, a step for depositing a transition metal on the cross-section, a first heat treatment step for heating the sample to form an alloy of the semiconductor and the transition metal on the cross-section, a first immersion step for immersing the sample in solution containing hydrogen peroxide solution, a second heat treatment step for heating the sample after the first immersion step and accelerating the alloying reaction, a second immersion step for immersing the sample in solution containing hydrofluoric acid and etching the alloy, and a step for detecting the junction interface by observing the etching state of alloy in the P-type impurity region and the N-type impurity region.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过预测和控制晶体管的器件特性并执行特定部分的缺陷分析来检测微型半导体器件的半导体衬底中的PN结的位置的方法。解决方案：用于检测半导体衬底上的P型杂质区域和N型杂质区域的结位置的方法包括通过暴露观察对象的横截面来制造样品的步骤，步骤用于清洁横截面的步骤，用于在横截面上沉积过渡金属的步骤，用于加热样品以在横截面上形成半导体和过渡金属的合金的第一热处理步骤，第一浸渍步骤用于将样品浸渍在含有过氧化氢溶液的溶液中，第二热处理步骤，用于在第一浸渍步骤之后加热样品并加速合金化反应;第二浸渍步骤，用于将样品浸入含有氢氟酸的溶液中并蚀刻合金; 通过观察P型杂质区域和N型杂质区域中的合金的蚀刻状态来检测接合界面的步骤。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2008004594A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008004594A
公开(公告)日：2008-01-10
申请号：JP2006169766
申请日：2006-06-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAINO KANTA
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66621 , H01L21/28035 , H01L27/10876 , H01L27/10894 , H01L29/4236
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having a trench-type MOSFET in which the concentration of impurities of a silicon electrode layer is improved near the bottom of the trench.
SOLUTION: The manufacturing method successively has a process of forming a trench 13 on the surface of a silicon substrate 11; a process of forming a gate insulating film 14 on the surface of the trench 13; a process of depositing silicon electrode layer 17 having an oxygen mixing layer formed in parallel to the surface of the trench 13, on the surface of the gate insulating film 14 in the trench 13; a process of doping impurities into the silicon electrode layer 17; and a process of executing heat treatment for the silicon electrode layer 17 to diffuse the impurities.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有沟槽型MOSFET的半导体器件的制造方法，其中在沟槽底部附近改善了硅电极层的杂质浓度。解决方案：该制造方法依次具有在硅衬底11的表面上形成沟槽13的工艺; 在沟槽13的表面形成栅极绝缘膜14的工序; 在沟槽13中的栅极绝缘膜14的表面上沉积具有与沟槽13的表面平行形成的氧混合层的硅电极层17的工序; 将杂质掺杂到硅电极层17中的工序; 以及对硅电极层17进行热处理以扩散杂质的处理。版权所有（C）2008，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式