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    • 7. 发明公开
    • HALBLEITERANORDNUNG MIT GEKOPPELTEN SPERRSCHICHT- FELDEFFEKTTRANSISTOREN
    • 耦合结型场效应晶体管功率半导体装置
    • EP2067170A1
    • 2009-06-10
    • EP07820405.4
    • 2007-09-20
    • SiCED Electronics Development GmbH & Co KG
    • FRIEDRICHS, PeterSTEPHANI, Dietrich
    • H01L27/098H03K17/082H01L27/02H01L29/808
    • H01L27/098H01L27/0248H01L29/8083H03K17/0822H03K17/6877
    • The invention relates to a semiconductor arrangement, comprising a first depletion layer field effect transistor and a second first depletion layer field effect transistor, wherein each depletion layer field effect transistor comprises a semiconductor body (116) of the one conductor type, which is in contact with a source electrode (S1; S2) and a drain electrode (D) spaced from the same such that between the source electrode and the drain electrode a flow path in created in the semiconductor body, and zones (117, 139, 122; 140, 128, 124) of the other conductor type that is opposite from the one conductor type, wherein the zones are provided in the region of the flow path in the semiconductor body and are in contact with a gate electrode (G1; G2) and form space charge regions controlling the flow path in the semiconductor body (116). The drain electrodes of the two depletion layer field effect transistors are short-circuited, and the source electrode (S1) of the first field effect transistor is short circuited with the gate electrode (G2) of the second depletion layer field effect transistor. The invention further relates to a circuit arrangement comprising this semiconductor arrangement, which has a switch element (104) that is controlled by the potential of the source electrode (S2) of the second depletion layer field effect transistor. The switch element can connect the gate electrode (G1) and the source electrode (S1) of the first depletion layer field effect transistor with a potential difference increasing the space charge regions.
    • 9. 发明公开
    • SCR Type memory apparatus
    • Speichergerger von SCR-Typ。
    • EP0530623A2
    • 1993-03-10
    • EP92114347.5
    • 1992-08-21
    • SONY CORPORATION
    • Mogi, Takayuki
    • G11C11/414H01L27/098
    • G11C11/415G11C11/4116H01L27/1025
    • The SCR type memory apparatus of the invention is short in access time, the current values upon reading and writing are easy to set and the construction of a peripheral circuit becomes simple with less power supply voltage limitation. The apparatus comprises a basic cell circuit with a SCR type memory cell (21) including a pair of pnp transistors and a pair of double emitter transistors and a pair of write npn transistors (23) in addition. The collector of each of the write npn transistors is connected to a voltage holding node (22) of the SCR type memory cell (21) and the bases are connected to a word selecting line (UWL).
    • 本发明的SCR型存储装置的访问时间短,读写时的电流值容易设定,外围电路的构造变得简单,电源电压限制较小。 该装置包括具有包括一对pnp晶体管和一对双发射极晶体管和一对写入npn晶体管(23)的SCR型存储单元(21)的基本单元电路。 每个写npn晶体管的集电极连接到SCR型存储单元(21)的电压保持节点(22),并且基极连接到字选择线(UWL)。