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1. 发明授权

EP3574584B1 VARIABLE DELAY CIRCUITS 有权
公开(公告)号：EP3574584B1
公开(公告)日：2024-01-24
申请号：EP17701314.1
申请日：2017-01-24
发明人： MU, Fenghao
IPC分类号： H03K5/134 , H03K3/356

2. 发明公开

EP4024707A2 DELAY LINE STRUCTURE AND DELAY JITTER CORRECTION METHOD THEREOF 审中-公开
公开(公告)号：EP4024707A2
公开(公告)日：2022-07-06
申请号：EP21210896.3
申请日：2021-11-26
申请人： Suzhou Motorcomm Electronic Technology Co., Ltd.
发明人： LIU, Yahuan
IPC分类号： H03K5/131 , H03K5/134 , H03K5/1252 , H03K5/15
摘要： The invention discloses a delay line structure and a delay jitter correction method thereof. The delay line structure comprises N delay units and N selectors. An output end of the N-1th delay unit is connected to a first input end of the N-1th selector and an input end of the Nth delay unit respectively, the N-1th selector inputs the N-1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N-1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals. According to the invention, delay control can be carried out on the clock at the sending end or the receiving end to meet the requirement of receiving timing, and the jitter of the delay of the delay line can be reduced.

3. 发明授权

EP3267585B1 PHASE DETECTOR FOR CLOCK DATA RECOVERY CIRCUIT 有权
公开(公告)号：EP3267585B1
公开(公告)日：2020-04-01
申请号：EP16200684.5
申请日：2016-11-25
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Lee, Yeong-Sheng
IPC分类号： H03D13/00 , H03K5/134 , H03L7/085 , H03L7/087 , H04L7/033 , H03K5/00

4. 发明公开

EP3038257A4 RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD 有权
标题翻译： REKONFIGURIERBAREVERZÖGERUNGSSCHALTUNG，VERZÖGERUNGSMONITORSCHALTUNGUNTER VERWENDUNG DER BESAGTENVERZÖGERUNGSSCHALTUNG，VARIATIONSKORREKTURSCHALTUNG，VARIATIONSMESSVERFAHREN UND VARIATIONSKORREKTURVERFAHREN
公开(公告)号：EP3038257A4
公开(公告)日：2017-08-09
申请号：EP14838727
申请日：2014-07-29
申请人： JAPAN SCIENCE & TECH AGENCY
发明人： ONODERA HIDETOSHI , A K M MAHFUZUL ISLAM
IPC分类号： H03K5/134 , G01R31/28 , H03K3/03 , H03K5/04
CPC分类号： H03K5/134 , G01R31/2882 , H03K2005/00019
摘要： A delay circuit (10) contains a first inversion circuit including a pull-up circuit (2) and a pull-down circuit (3), and a second inversion circuit including a pull-up circuit (4) and a pull-down circuit (5). The delay circuit further contains a first pass transistor (6) connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node (Out), a second pass transistor (7) connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor (8) connected in series between the input node (In) and the pull-up circuit in the second inversion circuit, and a fourth pass transistor (9) connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals (C1 to C4) applied to gates of the first to fourth pass transistors.
摘要翻译：延迟电路（10）包含具有上拉电路（2）和下拉电路（3）的第一反相电路以及包括上拉电路（4）和下拉电路（3）的第二反相电路（5）。延迟电路还包括串联连接到电源电位和输出节点（Out）之间的第一反相电路中的上拉电路的第一传输晶体管（6），串联连接到第二传输晶体管在地电位和输出节点之间的第一反相电路中的下拉电路，串联连接在输入节点（In）和第二反相电路中的上拉电路之间的第三传输晶体管（8），以及第四传输晶体管（9）串联连接在第二反相电路中的输入节点和下拉电路之间。通过施加到第一至第四通过晶体管的栅极的控制信号（C1至C4）的组合来改变延迟电路的延迟特性。

5. 发明授权

EP4033312B1 CONTROL CIRCUIT AND DELAY CIRCUIT 有权
公开(公告)号：EP4033312B1
公开(公告)日：2024-08-21
申请号：EP21772658.7
申请日：2021-05-24
IPC分类号： G05B19/042 , H03K5/134 , G05F3/20 , H03K5/00
CPC分类号： H03K2005/0001320130101 , G05B19/042 , H03K5/134 , G05F3/205

6. 发明授权

EP3998705B1 DELAY CIRCUIT AND DELAY STRUCTURE 有权
公开(公告)号：EP3998705B1
公开(公告)日：2024-07-10
申请号：EP21777918.0
申请日：2021-06-01
IPC分类号： H03K5/13 , H03K5/134 , H03K5/00
CPC分类号： H03K5/134 , H03K2005/0019520130101 , H03K2005/0012320130101 , H03K5/00 , H03K5/13

8. 发明公开

EP3048727A4 DELAY CIRCUIT, OSCILLATION CIRCUIT, AND SEMICONDUCTOR DEVICE 有权转让
标题翻译： VERZÖGERUNGSSCHALTUNG，OSZILLATIONSSCHALTUNG和UNDHALBLEITERBAUELEMENT
公开(公告)号：EP3048727A4
公开(公告)日：2017-07-05
申请号：EP14817340
申请日：2014-06-20
申请人： SII SEMICONDUCTOR CORP
发明人： NIHEI YOTARO , YOKOYAMA TOMOYUKI
IPC分类号： H03K5/134 , H03B5/26
CPC分类号： H03K5/12 , H03B5/24 , H03B5/26 , H03K5/134
摘要： Provided is a voltage regulator, wherein power consumption is small, and an NMOS transistor is used as an output transistor. This delay circuit is configured by providing, between a constant current circuit and a capacitor, a depression NMOS transistor having the gate and the back gate thereof connected to a ground terminal, said constant current circuit being configured from a depression NMOS transistor and a resistor that is provided between the gate and the back gate, and the source of the depression NMOS transistor.
摘要翻译：提供一种电压调节器，其中功耗较小，并且NMOS晶体管用作输出晶体管。该延迟电路通过在恒定电流电路和电容器之间设置使栅极和背栅极与接地端子连接的凹陷型NMOS晶体管构成，所述恒定电流电路由凹陷型NMOS晶体管和电阻构成，设置在栅极和背栅极之间，以及凹陷NMOS晶体管的源极。

9. 发明公开

EP3073528A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：EP3073528A1
公开(公告)日：2016-09-28
申请号：EP16158030.3
申请日：2016-03-01
申请人： Renesas Electronics Corporation
发明人： OKAGAKI, Takeshi
IPC分类号： H01L27/02 , H01L27/092 , H03K5/134 , H01L23/522
CPC分类号： H01L27/0924 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L29/0657 , H03K5/134
摘要： The semiconductor device includes a first inverter (10) and a second inverter (20) which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.
摘要翻译：该半导体器件包括串联连接的第一反相器（10）和第二反相器（20）。第一和第二反相器中的每一个分别包括p沟道晶体管和n沟道晶体管。分别作为第二反相器的p沟道和n沟道晶体管的有源区域的投影半导体层的数量小于各自作为p沟道和n沟道的有源区域的投影半导体层的数量，第一反相器的沟道晶体管。

10. 发明公开

EP3038257A1 RECONFIGURABLE DELAY CIRCUIT, DELAY MONITOR CIRCUIT USING SAID DELAY CIRCUIT, VARIATION CORRECTION CIRCUIT, VARIATION MEASUREMENT METHOD, AND VARIATION CORRECTION METHOD 有权
标题翻译：可重构延时电路，延迟电路监视使用所述延迟电路，变化的修正电路，变化测量方法和变化的校正方法
公开(公告)号：EP3038257A1
公开(公告)日：2016-06-29
申请号：EP14838727.7
申请日：2014-07-29
申请人： Japan Science and Technology Agency
发明人： ONODERA, Hidetoshi , A.K.M MAHFUZUL, Islam
IPC分类号： H03K5/134 , H03K5/04 , H03K3/03 , G01R31/28
摘要： A delay circuit (10) contains a first inversion circuit including a pull-up circuit (2) and a pull-down circuit (3), and a second inversion circuit including a pull-up circuit (4) and a pull-down circuit (5). The delay circuit further contains a first pass transistor (6) connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node (Out), a second pass transistor (7) connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor (8) connected in series between the input node (In) and the pull-up circuit in the second inversion circuit, and a fourth pass transistor (9) connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals (C1 to C4) applied to gates of the first to fourth pass transistors.
摘要翻译：延迟电路（10）包含一个第一反转电路包括上拉电路（2）和一个下拉电路（3），以及第二反相电路包括上拉电路（4）和一个下拉电路（5）。延迟电路还含有一个电源电位（输出），（7）串联连接到第二传输晶体管之间，并且输出节点串联连接到所述上拉电路的第一反相电路的第一传输晶体管（6）在一个接地电位和所述输出节点，所述输入节点之间串联连接的第三传输晶体管（8）（in）和在所述第二反相电路的上拉电路，和一个之间的第一反相电路的下拉电路串联连接在输入节点和所述第二反相电路的下拉电路之间串联第四传输晶体管（9）。所述延迟电路的延迟特性由施加到第一的栅极至第四通晶体管的控制信号的（C1至C4）的组合改变。

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