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1. 发明公开

EP4333333A1 TRANSMITTER, RECEIVER, PARAMETER ADJUSTMENT METHOD, SERDES CIRCUIT AND ELECTRONIC DEVICE 审中-实审
公开(公告)号：EP4333333A1
公开(公告)日：2024-03-06
申请号：EP21943560.9
申请日：2021-06-03
申请人： Huawei Technologies Co., Ltd.
发明人： ZHANG, Bingzhao , CHEN, Yanqin , QIAN, Zhaohua , CHEN, Hangzhou , KE, Jiandong , WANG, Guizhen , TAN, Lijuan
IPC分类号： H04L1/00 , H04L25/00
摘要： This application relates to the communication field, and discloses a transmitting apparatus, a receiving apparatus, a parameter adjustment method, a SerDes circuit, and an electronic device, to reduce a time required for adjusting a transmission parameter A transmitting apparatus includes a signal generation circuit and an adjustment circuit. The signal generation circuit is configured to send, to a receiving apparatus, a serial data signal that carries a training sequence or valid data, where the training sequence is used to train a skew or an equalization of the serial data signal, and the valid data is used to detect an amplitude of the serial data signal. The adjustment circuit is configured to: receive indication information from the receiving apparatus, and adjust a transmission parameter of the serial data signal based on the indication information, where the transmission parameter includes at least one of the skew, the equalization, or the amplitude of the serial data signal.

2. 发明公开

EP4106205A1 PHASE-LOCKED LOOP CIRCUIT 审中-公开
公开(公告)号：EP4106205A1
公开(公告)日：2022-12-21
申请号：EP20922722.2
申请日：2020-03-03
申请人： Huawei Technologies Co., Ltd.
发明人： CHEN, Yanqin
IPC分类号： H03L7/089
摘要： A phase-locked loop circuit includes a phase frequency detector (11), a first voltage control module (12), a second voltage control module (13), a third voltage control module (14), a voltage-controlled oscillator (15), and a frequency divider (16). A first output end (111) of the phase frequency detector (11) is connected to a first input end (121) of the first voltage control module (12) and a first input end (131) of the second voltage control module (13), a second output end (112) of the phase frequency detector (11) is connected to a second input end (122) of the first voltage control module (12) and a second input end (132) of the second voltage control module (13), an output end (123) of the first voltage control module (12) and an output end (133) of the second voltage control module (13) are separately connected to an input end (141) of the third voltage control module (14), an output end (142) of the third voltage control module (14) is connected to an input end (151) of the voltage-controlled oscillator (15), an output end (152) of the voltage-controlled oscillator (15) is connected to an input end (161) of the frequency divider (16), and an output end (162) of the frequency divider (16) is connected to an input end (113) of the phase frequency detector (11). The phase frequency detector (11) is configured to detect a phase difference between a reference signal and a feedback signal. The first voltage control module (12) is configured to obtain a low-frequency component of a reference control voltage. The second voltage control module (13) is configured to obtain a high-frequency component of the reference control voltage. The third voltage control module (14) is configured to adjust the high-frequency component and the low-frequency component of the reference control voltage to obtain a target control voltage, where the target control voltage is processed by the voltage-controlled oscillator (15) and the frequency divider (16) to obtain the feedback signal.

3. 发明公开

EP4300826A1 INTERFACE CIRCUIT AND CONTROL METHOD THEREOF, CHIP, TERMINAL DEVICE 审中-实审
公开(公告)号：EP4300826A1
公开(公告)日：2024-01-03
申请号：EP21930774.1
申请日：2021-03-17
申请人： Huawei Technologies Co., Ltd.
发明人： QIAN, Zhaohua , WANG, Jingjing , CHEN, Yanqin , KE, Jiandong
IPC分类号： H03K19/0175
摘要： An interface circuit, a method for controlling the interface circuit, a chip, and a terminal device are provided, to avoid a problem of current backflow. The interface circuit includes a first PMOS transistor, an input signal control circuit (10), a bias circuit (20), a signal input end, and an input/output end. The bias circuit (20) includes a substrate bias voltage generation end and a bias voltage generation end. The bias circuit (20) is coupled to a high-level power supply end, the input/output end, and a ground end. The input signal control circuit (10) is connected to the signal input end, the bias voltage generation end, and a gate of the first PMOS transistor; a first electrode of the first PMOS transistor is connected to the high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input/output end; the substrate bias voltage generation end is connected to a substrate of the first PMOS transistor; the input signal control circuit (10) is configured to transmit an electrical signal of the signal input end or an electrical signal of the bias voltage generation end to the gate of the first PMOS transistor; and the bias circuit (20) is configured to perform connection and conduction between the high-level power supply end or the input/output end and the substrate bias voltage generation end.

4. 发明公开

EP3982535A1 RC OSCILLATOR 审中-公开
公开(公告)号：EP3982535A1
公开(公告)日：2022-04-13
申请号：EP19936257.5
申请日：2019-06-29
申请人： Huawei Technologies Co., Ltd.
发明人： CHEN, Yanqin , WU, Chunbiao , LIU, Yongwang , ZHANG, Bingzhao
IPC分类号： H03B5/04 , H03K3/013
摘要： Embodiments of this application disclose an RC oscillator. The RC oscillator may amplify a difference between a first voltage and a second voltage by using a first amplifier and a second amplifier. The first amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit and the second amplification circuit may share a same voltage-current conversion circuit. The RC oscillator disclosed in the embodiments of this application can not only avoid noise introduced by the first amplifier, but also reduce internal noise of the RC oscillator. This reduces a jitter of a clock signal.

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