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1. 发明授权

EP0006471B1 Disk file controller 失效
标题翻译：磁盘文件控制器
公开(公告)号：EP0006471B1
公开(公告)日：1982-03-17
申请号：EP79101703.1
申请日：1979-06-01
申请人： International Business Machines Corporation
发明人： Carlton, James Earnest , Schaeuble, Werner Josef
IPC分类号： G06F13/04 , G06F5/04 , G11B5/012
CPC分类号： G06F3/0601 , G06F2003/0692

2. 发明公开

EP0119689A2 Serial and parallel interface device 失效
标题翻译： Serien- und Parallelschnittstelleneinrichtung。
公开(公告)号：EP0119689A2
公开(公告)日：1984-09-26
申请号：EP84300404.5
申请日：1984-01-24
申请人： NORTHERN TELECOM LIMITED
发明人： Aczel, Andreas Laszlo , Watchorn, James Leslie , Wong, Edmund Pea Fu
IPC分类号： G06F5/04 , H03M9/00
CPC分类号： H03M9/00
摘要： An interface device (110) for converting serial data to parallel data and vice-versa is disclosed. The interface device (110) is comprised of a plurality of storage elements (SE) electrically interconnected into an array (113) having an equal number of rows and columns. Each storage element comprises a storage device (116) and two switching devices (117, 118) for selectively applying data from one of two inputs (A, E) of the storage element (SE) to the storage device (116). As a result, data can be shifted through the array either along rows or along columns. The data, for a serial to parallel conversion, is shifted either along rows or columns of the array and is removed from the array, either one parallel word per time, one bit per each column of the array, or one parallel word per time, one bit per each row of the array. For a parallel to serial conversion, parallel data is applied sequentially to the array, either one bit per row or one bit per column of the array. This data is then removed from the array in a serial fashion either one bit stream per each column of the array or one bit stream per each row of the array.
摘要翻译：公开了一种用于将串行数据转换成并行数据的接口装置（110），反之亦然。接口装置（110）由多个存储元件（SE）组成，多个存储元件（SE）电互连成具有相等数量的行和列的阵列（113）。每个存储元件包括存储设备（116）和用于选择性地将数据从存储元件（SE）的两个输入（A，E）之一施加到存储设备（116）的开关设备（117,118）。因此，数据可以沿着行或沿列移动通过数组。用于串行到并行转换的数据沿数组的行或列移动，并从数组中移除，每个时间一个并行字，每个数组的每一列一个位，或每个时间一个并行字，阵列每行一位。对于并行到串行转换，并行数据顺序应用于阵列，每行一位或每列数组一位。然后，该数据以串行方式从数组的每列中的一个位流或阵列的每一行的一个位流中排除。

3. 发明授权

EP0006468B1 Parallel to series data converters 失效
标题翻译：并行数据转换器
公开(公告)号：EP0006468B1
公开(公告)日：1982-12-15
申请号：EP79101695.9
申请日：1979-06-01
申请人： International Business Machines Corporation
发明人： Allen, Francis Kempton , Chin, Victor Huie
IPC分类号： G06F5/04 , H04L25/45
CPC分类号： H04L25/45 , H03M9/00

4. 发明公开

EP0006471A1 Disk file controller 失效
标题翻译：磁盘文件控制器
公开(公告)号：EP0006471A1
公开(公告)日：1980-01-09
申请号：EP79101703.1
申请日：1979-06-01
申请人： International Business Machines Corporation
发明人： Carlton, James Earnest , Schaeuble, Werner Josef
IPC分类号： G06F13/04 , G06F5/04 , G11B5/012
CPC分类号： G06F3/0601 , G06F2003/0692
摘要： The invention concerns a disk file controller for the transfer of data from a parallel by bit interface to a serial by bit disk file interface.
A data channel has a data register (9), serializing and deserializing means (50 and 53) and a variable frequency oscillator to transfer parallel by bit data received by the register (9) from a DCI BUS OUT to be recorded serially by bit on a disk file. Alternatively the data channel receives serial by bit data read from a disk file and transfers it through the data register (9) in parallel by bit form to a DCI BUS lN. The several units of the data channel are controlled by a control register (28) supplied from a microprocessor (6). The microprocessor receives data selectively from the DCI BUS OUT and from the data register (9). Changes in format of the disk file data can be accommodated by the microprocessor (6) without need to change special purpose formatting hardware.
摘要翻译：本发明涉及一种磁盘文件控制器，用于将数据从并行逐位接口传送到逐位磁盘文件接口。一个数据通道有一个数据寄存器（9），串行和解串行装置（50和53）以及一个可变频率振荡器，用于通过寄存器（9）从DCI总线OUT接收的位数据并行传送，一个磁盘文件。或者，数据通道接收从磁盘文件中读取的逐位数据，并通过位形式将其通过数据寄存器（9）并行传输到DCI总线。数据通道的几个单元由从微处理器（6）提供的控制寄存器（28）控制。微处理器有选择地从DCI BUS OUT和数据寄存器（9）接收数据。微处理器（6）可以适应磁盘文件数据格式的改变，而不需要改变专用格式化硬件。

5. 发明公开

EP0006468A2 Parallel to series data converters 失效
标题翻译： Parallel-Serienumsetzung von Daten。
公开(公告)号：EP0006468A2
公开(公告)日：1980-01-09
申请号：EP79101695.9
申请日：1979-06-01
申请人： International Business Machines Corporation
发明人： Allen, Francis Kempton , Chin, Victor Huie
IPC分类号： G06F5/04 , H04L25/45
CPC分类号： H04L25/45 , H03M9/00
摘要： The converter comprises a data source (10) from which half-bytes of data are supplied in a parallel-by-bit, serial-by-half-byte manner to data registers (14, 16). The supply is controlled by control logic (18) so that register (14) is being filled while register (16) is being emptied and vice versa. Data from the registers (14, 16) are supplied to steering circuits (28, 30, 32, 34) which act as gating circuits. Circuits (28, 30) are gated by a first signal taken from counter (20) and circuits (32, 34) by a second signal taken from the counter. The first and second signals are in anti-phase and are operative so that in one quarter cycle bits (0, 1) are gated through circuits (28, 30); in the second quarter cycle bits (2, 3) are gated through circuits (32, 34); in the third quarter cycle bits (4, 5) are gated through circuits (28, 30); and in the fourth quarter cycle bits (6, 7) are gated through circuits (32, 34). The sample and interleave circuit (36) receives the signals gated through circuits (28, 30, 32, 34) and is operative, under the control of sample (A, B, C, D) timing signals, to sample and gate to a common output line, the outputs of the circuits (28, 30; 32, 34; 28, 30; 32, 34) during the four quarter cycles, two sampling being made serially every quarter cycle.
摘要翻译：该转换器包括数据源（10），半字节的数据以逐个字节的逐字节方式提供给数据寄存器（14,16）。供应由控制逻辑（18）控制，使得寄存器（14）正在被填充，而寄存器（16）被清空，反之亦然。来自寄存器（14,16）的数据被提供给用作选通电路的转向电路（28,30,32,34）。电路（28,30）由从计数器（20）和电路（32,34）取得的第一信号通过从计数器取出的第二信号来选通。第一和第二信号是反相的并且是可操作的，使得在四分之一周期中，位（0,1）通过电路（28,30）选通; 在第二季度周期中，位（2,3）通过电路（32,34）选通; 在第三季度周期中，位（4,5）通过电路（28,30）进行门控; 并且在第四个四分之一周期中，位（6,7）通过电路（32,34）选通。采样和交织电路（36）接收通过电路（28,30,32,34）门控的信号，并且在样本（A，B，C，D）定时信号的控制下操作，以采样和门控到公共输出线，在四个四分之一周期期间电路（28,30; 32,34; 28,30; 32,34）的输出，每四个周期进行两次采样。

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