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1. 发明公开

EP2413554A2 Vorrichtung zur Manipulation von Schnittstellensignalen 有权
公开(公告)号：EP2413554A2
公开(公告)日：2012-02-01
申请号：EP11164538.8
申请日：2011-05-03
申请人： Dr. Johannes Heidenhain GmbH
发明人： Kreuzer, Stephan, Dr. , Mayer, Elmar, Dr. , Ollert, Udo
IPC分类号： H04L25/45 , G05B19/414 , G08C19/28 , H03M7/16
CPC分类号： H04L25/45 , G05B19/0428 , G05B19/406 , G05B19/414 , G05B23/0256 , H04Q9/00 , H04Q2209/43 , H04Q2209/75
摘要： Die vorliegende Erfindung betrifft eine Vorrichtung zur Manipulation von Schnittstellensignalen, mit
● einer Slave-Schnittstelle (12), die an eine Master-Schnittstelle (22) eines Steuergeräts (20) anschließbar ist,
● einer Master-Schnittstelle (18), die an eine Slave-Schnittstelle (32) eines Messgeräts (30) anschließbar ist,
● einer Schaltungsanordnung (15), der je Schnittstelle (12, 18) wenigstens ein Dateneingangsignal (DIN_S, DIN_M) zugeführt ist und die je Dateneingangssignal (DIN_S, DIN_M) zur jeweils anderen Schnittstelle (12, 18) ein korrespondierendes Datenausgangssignal (DOUT_M, DOUT_S) ausgibt, wobei

die Schaltungsanordnung (15) wenigstens eine Manipulationseinheit (110, 120) umfasst, der ein Dateneingangssignal (DIN_S, DIN_M) und ein Ersatzdatensignal (DE_S, DE_M) zugeführt ist und die ein korrespondierendes Datenausgangssignal (DOUT_M, DOUT_S) ausgibt, sowie eine Protokolleinheit (100), der wenigstens ein protokollrelevantes Schnittstellensignal (DIN_S, DIN_M, TCLK_S) zugeführt ist und die anhand von Manipulationsregeln und mit dem wenigstens einen protokollrelevanten Schnittstellensignal (DIN_S, DIN_M, TCLK_S) empfangenen Informationen auswählt, wann die wenigstens eine Manipulationseinheit (110, 120) als Datenausgangssignal (DOUT_M, DOUT_S) das korrespondierende Dateneingangssignal (DIN_S, DIN_M) oder das Ersatzdatensignal (DE_S, DE_M) ausgibt. ( Figur 1 )
摘要翻译：设备（10）具有连接到控制设备（20）的主接口（22）的从接口（12）。电路结构（15）包括操作单元，其中数据输入信号（DIN-M，DIN-S）和替代数据信号被提供给操作单元，该操作单元输出相应的数据输出信号（DOUT-M，DOUT -S）。当操作单元输出相应的数据输入信号或替代数据信号作为数据输出信号时，协议相关接口信号被发送到协议单元并且基于操纵规则和信息来选择。还包括用于包括接口控制器的控制设备的独立权利要求。

2. 发明公开

EP2053813A3 Data transmission 审中-公开
标题翻译：数据传输
公开(公告)号：EP2053813A3
公开(公告)日：2010-12-08
申请号：EP08253250.8
申请日：2008-10-07
申请人： Tektronix Inc.
发明人： Hazzard, Shane A. , Tran, Que Thuy , Klingman, Kayla R. , Kelly, David L. , Smith, Patrick A. , Knierim, Daniel G.
IPC分类号： H04L25/45 , H04L25/05 , H04L25/14 , H04L25/49
CPC分类号： H03M9/00 , H04J3/076 , H04L25/14 , H04L25/4908
摘要： Serial data is input to a transmitter, where it is demultiplexed into a plurality of multi-bit lanes, e.g. n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section.
In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.

3. 发明公开

EP1662657A4 RECEIVER CIRCUIT, INTERFACE CIRCUIT AND ELECTRONIC DEVICE 有权
标题翻译：接收电路，接口电路和电子设备撕扯
公开(公告)号：EP1662657A4
公开(公告)日：2007-01-03
申请号：EP04787637
申请日：2004-09-06
申请人： SEIKO EPSON CORP
发明人： SHIBATA YUKINARI , SAITO NOBUYUKI , HASEGAWA TOMONAGA , ISHIDA TAKUYA
IPC分类号： G06F3/00 , H04L25/03 , G06F13/40 , H03K5/1252 , H03K19/00 , H03K19/0175 , H03L5/00 , H04B1/16 , H04L25/02 , H04L25/45
CPC分类号： H04L25/45 , H04L25/0292
摘要： A receiver circuit includes a current/voltage converter circuit for performing, based on currents flowing through differential signal lines, current/voltage conversions to output voltage signals; a comparator for comparing the voltage signals to output an output signal; a power down detector circuit for detecting, based on a comparison result in the comparator, a power down command when a transmitter circuit current drives the differential signal lines to thereby transmit the power down command in a normal transfer mode; and a power down setting circuit for setting at least one of the current/voltage converter circuit and the comparator to the power down mode when the power down command is detected.

4. 发明公开

EP1289214A3 Data communication system, controller device and data communication method 审中-公开
标题翻译：的数据传输系统中，控制器和数据传输方法
公开(公告)号：EP1289214A3
公开(公告)日：2006-11-08
申请号：EP02018246.5
申请日：2002-08-21
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Inoue, Atsuo , Nakashima, Shota
IPC分类号： H04L25/45
CPC分类号： H04L25/45
摘要： In a controller device, when a first transmitting signal is at a "L" level, a first operation voltage is high and the amplitude of signals CK and ICK is large, and on the contrary, the amplitude is small when the first transmitting signal is at a "H" level. In a data carrier device, the signals CK and ICK are subjected to full-wave rectification by a rectifier circuit so as to generate a second operation voltage, and a first receiving signal is extracted from the second operation voltage by a first signal detection circuit. On the other hand, in the data carrier device, when a second transmitting signal is at a "L" level, impedance between two contacts is small and the amplitude of the signals CK and ICK is small, and on the contrary, the amplitude is large when the second transmitting signal is at a "H" level. In the controller device, change of the amplitude of the signal ICK is extracted as a second receiving signal by a second signal detection circuit. Accordingly, supply of power and clock and two-way serial data communication can be simultaneously executed between the controller device and the data carrier device through merely two contacts.

5. 发明授权

EP1104612B1 DATA-COMMUNICATIONS UNIT SUITABLE FOR ASYNCHRONOUS SERIAL DATA TRANSMISSION 有权
标题翻译：数据传输单元异步串行数据传输
公开(公告)号：EP1104612B1
公开(公告)日：2003-08-27
申请号：EP99941626.6
申请日：1999-08-11
申请人： Koninklijke KPN N.V.
发明人： ROOS VAN RAADSHOOVEN, Leonard, Antonius , PIETERSE, Rob
IPC分类号： H04L25/45 , G06F13/12 , G06F13/38
CPC分类号： H04L25/45 , G06F13/126 , G06F13/385
摘要： Data-communications unit suitable for asynchronous serial data transmission between a data-processing device and a peripheral device, such as a modem, having, for one or either transmission direction, at least one First-In, First-Out memory (FIFO) for data and for management data, with a view to transmitting and indicating the status of the peripheral device. The FIFO or FIFOs associated with a transmission direction are controlled in such a manner that a sequence of data received by the data-communications unit (irrespective of the type) is maintained at the output side thereof.

6. 发明公开

EP0122870A2 Enhanced distance data transmission system 失效
标题翻译： DatenübertragungssystemfürvergrösserteEntfernung。
公开(公告)号：EP0122870A2
公开(公告)日：1984-10-24
申请号：EP84630061.4
申请日：1984-04-17
申请人： MEGABIT COMMUNICATIONS, INC.
发明人： Milligan, James H.
IPC分类号： G06F13/42 , H04L25/36 , H04L25/45 , H04L1/18
CPC分类号： H04L25/45 , G06F13/4226 , H04L1/1671 , H04L25/05
摘要： A logic system between parallel channel end devices such as a computer and peripheral device. A level converter converts parallel digital signals from the external devices to levels for the system. A comparator samples the converted levels. Multiplex serialization of the parallel signals in initiated by comparator action and proceeds under count control. Sampled converted levels are also used to generate mode signals which are used to select predetermined logic patterns within the system, and to select varied lengths of count for message serialized fortransmission from one end of the logic system to the other. The serialized messages received at the other end are converted to parallel form by a shift register under count action governed by the mode oftransmission. A sampling of the mode intelligence transmitted is used to set the receiving end in the same mode as the sending end. Buffer registers are provided for temporary storage of received messages. Special circuitry is adapted to generate signals from outputs of the external devices and turn those signals back to the external devices to enhance rapid data transfer. And logic circuitry is employed which provides the sending end of the system with intelligence on the availability of buffer storage space at the receiving end.
摘要翻译：平行通道终端设备（如计算机和外围设备）之间的逻辑系统。电平转换器将来自外部设备的并行数字信号转换为系统的电平。比较器对转换后的电平进行采样。通过比较器动作启动的并行信号的多路序列化，并在计数控制下进行。采样转换电平也用于产生用于选择系统内的预定逻辑模式的模式信号，并且为串行化用于从逻辑系统的一端传输到另一端的消息选择不同长度的计数。在另一端接收的串行消息由传输模式控制的计数动作下由移位寄存器转换为并行形式。发送模式智能的采样用于将接收端设置为与发送端相同的模式。提供缓冲寄存器用于临时存储接收到的消息。特殊电路适用于从外部设备的输出产生信号，并将这些信号转回外部设备，以增强快速的数据传输。并且采用逻辑电路，其提供在接收端对缓冲存储空间的可用性的智能发送端。

7. 发明公开

EP0112951A1 Procédé et dispositif de transmission de bits d'information entre microplaquettes 失效
标题翻译：微芯片之间传送的信息比特的方法和装置。
公开(公告)号：EP0112951A1
公开(公告)日：1984-07-11
申请号：EP82430045.3
申请日：1982-12-28
申请人： International Business Machines Corporation , Compagnie IBM FRANCE
发明人： Boudon, Gérard , Mollier, Pierre , Lebesnerais, Gérard
IPC分类号： H04L25/48 , H04L25/45
CPC分类号： H04L25/45 , H04L25/49
摘要： Dans la microplaquette émettrice, les bits sont sérialisés et appliqués à un codeur dans lequel le train de bits (D) et son complément ( D ) sont transformés en deux signaux (PH1 et PH2) sous contrôle d'un signal d'horloge en dents de scie CK'. Les signaux (PH1 et PH2) sont envoyés à la microplaquette réceptrice, les signaux (PH1 et PH2) sont appliqués à un décodeur qui engendre deux signaux ( DJ ) et (DK) représentatifs des bits de données et un signal d'horloge CLK reconstitué. Les trois signaux ( DJ , DK et CLK) ainsi qu'un signal de trame (F) sont utilisés par un circuit de conversion et de démultiplexage pour retrouver les multiplets de bits de données parallèles.

8. 发明公开

EP0094178A2 Interface for serial data communications link 失效
标题翻译：接口，用于串行数据传输线。
公开(公告)号：EP0094178A2
公开(公告)日：1983-11-16
申请号：EP83302412.8
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Stewart, Robert E. , Buzynski, John E. , Giggi, Robert
IPC分类号： H04L25/49 , H04L7/04 , H04L25/45 , G06F3/04
CPC分类号： H04L25/45 , G06F13/4213 , G06F13/423 , H04L7/042 , H04L25/4904
摘要： An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14,16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-ore gate (52), and at least one delay line (58A or 588) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

9. 发明公开

EP1446883A4 MULTIMODE CIRCUITRY SUPPORTING LOW INTERFERENCE SIGNALING SCHEMES FOR HIGH SPEED DIGITAL INTERFACES 有权
标题翻译：更符合-I / O电路麻烦ARMS信令快速数字接口支持计划
公开(公告)号：EP1446883A4
公开(公告)日：2010-05-05
申请号：EP02802339
申请日：2002-10-17
申请人： NOKIA CORP
发明人： RUHA ANTTI , RUOTSALAINEN TARMO , TERVALUOTO JUSSI-PEKKA
IPC分类号： H03K19/094 , H03K19/0185 , H03K19/173 , H03K19/177 , H04L25/02 , H04L25/45
CPC分类号： H04L25/0272 , H01L2224/48091 , H01L2224/49175 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H04L25/0264 , H04L25/0282 , H04L25/0294 , H04L25/45 , H01L2924/00014 , H01L2924/00

10. 发明公开

EP2053813A2 Data transmission 审中-公开
标题翻译：数据传输
公开(公告)号：EP2053813A2
公开(公告)日：2009-04-29
申请号：EP08253250.8
申请日：2008-10-07
申请人： Tektronix Inc.
发明人： Hazzard, Shane A. , Tran, Que Thuy , Klingman, Kayla R. , Kelly, David L. , Smith, Patrick A. , Knierim, Daniel G.
IPC分类号： H04L25/45
CPC分类号： H03M9/00 , H04J3/076 , H04L25/14 , H04L25/4908
摘要： Serial data is input to a transmitter, where it is demultiplexed into a plurality of multi-bit lanes, e.g. n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section.
In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.
摘要翻译：串行数据被输入到发射机，在那里它被解复用成多个多比特通道，例如，每个N通道有n位。然后将N个车道编码为字符，编码的N个车道每m个位具有m位，其中m> n。位填充用于调整数据速率和/或插入限定符。然后将填充的编码的N个通道多路复用到N个串行通道中，这些通道从发送器部分输出以输入到接收器部分。在接收器部分，N个通道被解串行，解码并输入到字识别器以生成触发事件信号。

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