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1. 发明授权

EP3481491B1 BIASING OF A CURRENT GENERATION ARCHITECTURE FOR AN IMPLANTABLE MEDICAL DEVICE 有权
公开(公告)号：EP3481491B1
公开(公告)日：2020-05-13
申请号：EP17768598.9
申请日：2017-09-06
申请人： Boston Scientific Neuromodulation Corporation
发明人： MARNFELDT, Goran, N. , WEISS, Philip, L. , WEERAKOON, Pujitha , WAGENBACH, David, M. , FELDMAN, Emanuel , GURURAJ, Kiran, K.
IPC分类号： A61N1/02 , A61N1/36 , G06F3/05

3. 发明公开

EP3527996A1 MESSANORDNUNG UND VERFAHREN ZUM MESSEN ELEKTRISCHER SIGNALE 有权
公开(公告)号：EP3527996A1
公开(公告)日：2019-08-21
申请号：EP18157336.1
申请日：2018-02-19
申请人： Siemens Aktiengesellschaft
发明人： Mieske, Frank , Herrmann, Hans-Joachim , Loerke, Matthias
IPC分类号： G01R19/25 , G06F3/05
摘要： Die Erfindung betrifft eine Messanordnung (21) mit zumindest zwei Messeingängen (22a-c) zum Erfassen von Signalen elektrischer Wechselgrößen, einer den Messeingängen (22a-c) nachgeordneten Abtasteinrichtung (23), mit der eine Abtastung der Signale unter Bildung digitaler Abtastwerte vorgenommen wird, und einer Taktnachführeinrichtung (24), die eine Anpassung eines von der Abtasteinrichtung (23) für die Abtastung verwendeten Abtasttaktes hinsichtlich der Frequenz des abzutastenden Signals vornimmt.
Um Signale elektrischer Wechselgrößen auch dann zuverlässig erfassen zu können, wenn sie unterschiedliche Frequenzen aufweisen, wird vorgeschlagen, dass die Abtasteinrichtung (23) dazu eingerichtet ist, zumindest zwei der Signale mit jeweils einem eigenen Abtasttakt abzutasten, wobei die Taktnachführeinrichtung (24) dazu eingerichtet ist, gleichzeitig für jedes dieser zumindest zwei Signale eine Anpassung des Abtasttaktes hinsichtlich der Frequenz des abzutastenden Signals vorzunehmen.
Die Erfindung betrifft auch ein entsprechendes Verfahren zum Messen elektrischer Signale.

4. 发明公开

EP3015971A1 A SYSTEM AND A METHOD OF DERIVING INFORMATION 有权
标题翻译：系统VERFAHREN ZUR INFORMATIONSABLEITUNG
公开(公告)号：EP3015971A1
公开(公告)日：2016-05-04
申请号：EP15191569.1
申请日：2015-10-27
申请人： Napatech A/S
发明人： Josiassen, René Krog , Kragh, Søren
IPC分类号： G06F3/05 , H04J3/06
CPC分类号： G06F1/04 , G06F3/05 , H04J3/0697
摘要： A system and a method of sampling an event signal using multiple clocking signals each provided in a separate candidate clock domain each of which also receives points in time from a master clock. From each candidate clock domain, clocked by the individual clocking signals, pairs of a received point in time and event signal value are fed to a master clock domain. In the master clock domain, the values of the event signal may be determined over time as a function of master clock time. This may be used for synchronizing operation in the master clock domain of e.g. packet time stamping with an overall time defined by the event signal. Using multiple clocking signals for the sampling, a much more precise sampling of the event signal is facilitated.
摘要翻译：一种使用多个时钟信号对事件信号进行采样的系统和方法，每个时钟信号在单独的候选时钟域中提供，每个时钟信号也从主时钟接收时间点。从由各个时钟信号计时的每个候选时钟域，接收到的时间点和事件信号值的对被馈送到主时钟域。在主时钟域中，事件信号的值可以随时间而被确定为主时钟时间的函数。这可以用于例如主时钟域中的同步操作。分组时间戳由事件信号定义的总时间。使用多个时钟信号进行采样，便于对事件信号进行更精确的采样。

5. 发明公开

EP2778804A4 CONTROL PROGRAM, CONTROL METHOD, AND CONTROL DEVICE 有权
标题翻译：控制程序，控制方法和控制设备
公开(公告)号：EP2778804A4
公开(公告)日：2016-02-10
申请号：EP12848170
申请日：2012-10-30
申请人： KOKUSAI KEISOKUKI KK
发明人： MATSUMOTO SIGERU , MIYASHITA HIROSHI , TASHIRO KAZUYOSHI , MURAUCHI KAZUHIRO
IPC分类号： G05B13/04 , G01M7/02 , G01M13/02 , G05B17/02 , G05B19/18 , G05B19/414 , G05D3/12 , G06F3/05 , G06F17/50 , H02K7/10 , H02P5/00
CPC分类号： G06F17/5086 , G01M7/022 , G01M7/025 , G01M13/025 , G05B17/02 , G05B19/414 , G05B2219/42163 , G05B2219/50218 , G05B2219/50229
摘要： A control device including a simulation unit configured to simulate behaviors of a virtual mechanical system, and a drive control unit configured to control driving of a plurality of servomotors based on the results of the simulation, is provided. The virtual mechanical system includes a first drive module, a first main shaft module connected to the first drive module, and a plurality of power transmission subsystems, each of which is connected to the first main shaft module and is associated with one of the plurality of servomotors respectively. Each of the power transmission subsystems includes a second drive module, a differential gear module including a main input shaft, an auxiliary input shaft, and an output shaft, and an output module. The main input shaft is connected with the first main shaft module, the auxiliary input shaft is connected with the second drive module via a first clutch module, and the output shaft is connected with the output module.

6. 发明授权

EP2321926B8 User specific resampling for access protection of digital content 有权
标题翻译：用户特定重采样的数字内容访问保护
公开(公告)号：EP2321926B8
公开(公告)日：2015-10-28
申请号：EP09810952.3
申请日：2009-09-03
申请人： 4473574 Canada Inc.
发明人： GAVRILENCO, Colin , THERIEN, Mathieu
IPC分类号： G11B20/00 , G11B20/10 , H04L9/14 , G06F3/05 , G06F21/31
CPC分类号： H04N21/4627 , G06F21/10 , G10L19/018 , G11B20/10037 , H04N21/44

7. 发明授权

EP2678758B1 PROVIDING A CORRECTED VIEW BASED ON THE POSITION OF A USER WITH RESPECT TO A MOBILE PLATFORM 有权
标题翻译：提供更正查看用户的立场的基础上由于移动平台
公开(公告)号：EP2678758B1
公开(公告)日：2015-01-28
申请号：EP12716737.7
申请日：2012-02-22
申请人： Qualcomm Incorporated
发明人： KIMBALL, Robert Howard
IPC分类号： G06T19/00 , G06F3/0346 , G06F3/05 , G06F3/01 , G02B27/00 , G06F3/00
CPC分类号： G06F3/012 , G02B27/0093 , G06F3/005 , G06F3/0346 , G06T19/006

8. 发明公开

EP2807546A1 ANWENDUNGSSPEZIFISCHER INTEGRIERTER SCHALTKREIS UND EINEN MESSUMFORMER MIT EINEM SOLCHEN SCHALTKREIS 有权转让
标题翻译：应用专用集成电路和与该电路中的转换器
公开(公告)号：EP2807546A1
公开(公告)日：2014-12-03
申请号：EP13700754.8
申请日：2013-01-21
申请人： Endress+Hauser GmbH+Co. KG
发明人： KARWECK, Lars , SPITZ, Andreas , BOULENGER, Yves , WAGNER, Richard , WINTER, Klaus , ZIERINGER, Thomas
IPC分类号： G06F3/05 , H03M1/00 , G06F1/32 , G01F23/14
CPC分类号： G06F3/05 , G01F1/34 , G01F23/14 , G06F1/324 , H03M1/1255 , Y02D10/126
摘要： An application-specific integrated circuit (ASIC) (1) comprises: analogue inputs (11) with analogue/digital converters (ADC
i ) (12), at least one digital signal processor (DSP) (13) having input registers (14) and output registers (15), wherein the analogue/digital converter(s) (ADC) sample(s) input signals (S
i ), which depend on current values of measurement variables, at sampling frequencies (f
Si ) and digitize said signals and provide the input registers of the digital signal processor with the digitized signals (SD
i ) at output frequencies (f
SD-out-i ), wherein the digital signal processor (DSP) processes the digitized signals (SD
i ) to form m conditioned signals (SP
j ) and provides said signals in the output registers of the digital signal processor (DSP), wherein the digital signal processor has a clock frequency (f
DSP ), wherein the signals (SP
j ) can also be output or read from the output registers at an output frequency (f
SP-out-j ), wherein one or more of the frequencies (f
SD-out-i , f
DSP , f
SP-out-j ) is/are variable according to the invention, wherein one or more of the frequencies (f
SD-out-i , f
DSP , f
SP-out-j ) is/are, in particular, variable independently of the other of said frequencies.

9. 发明公开

EP2672627A4 DATA PROCESSING METHOD, DATA PROCESSING SYSTEM AND RELEVANT EQUIPMENT 有权
标题翻译：数据处理，数据处理系统及其装置
公开(公告)号：EP2672627A4
公开(公告)日：2014-04-02
申请号：EP12741633
申请日：2012-01-19
申请人： HUAWEI TECH CO LTD
发明人： WANG YONG , SHI XIAOMING , LI GANG , SHAO ZHUFA
IPC分类号： H03M1/00 , G06F1/32 , G06F3/05
CPC分类号： G06F1/3253 , G06F1/3287 , G06F3/05 , Y02D10/151 , Y02D10/171
摘要： A data processing method, a data processing system, and relevant devices are provided, which are used to reduce system power consumption. The method in embodiments of the present invention includes: performing sampling on an analog signal to obtain an analog sample value; performing analog-to-digital conversion on the analog sample value to obtain a digital signal; dividing bits forming the digital signal into at least two bit groups; and turning off output of bits in at least one bit group if a preset turnoff condition is satisfied. A data processing system and relevant devices are further provided.

10. 发明授权

EP1290540B1 ANALOGUE TO DIGITAL SIGNAL CONVERSION 有权
标题翻译：模拟数字信号灯
公开(公告)号：EP1290540B1
公开(公告)日：2004-05-12
申请号：EP01947358.6
申请日：2001-06-11
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： HEYL, Christian , SJÖLANDER, Joachim
IPC分类号： G06F3/05
CPC分类号： G06F3/05
摘要： An analogue to digital converter has a settable trigger level that generates an interrupt signal for a CPU when a trigger condition is fulfilled.

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