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1. 发明公开

EP0178163A3 A dual access digital storage device 失效
标题翻译：双重访问数字存储设备
公开(公告)号：EP0178163A3
公开(公告)日：1988-09-14
申请号：EP85307225
申请日：1985-10-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Moller, Ole , Po Loi Chu, Paul
IPC分类号： G11C08/00
CPC分类号： G11C8/16 , G11C7/1075
摘要： A two read-port, two write-port register file on a single integrated circuit chip provides dual read/write access via either an "A"-side or "B"-side of a single array of adressable registers. Separate on-chip "A"-side or "B"-side multiplexers permit reading or writing of an independently adressed register according to the phase of the "A"-side or "B"-side clock. Writing can be selctively effected to either a high-order and/or a low-order byte within the addressed register. Unidirectional busses connect each register to each of the four ports. The register can be expanded to provide a four read-port, two write-port register file such as is required for the parallel computation of addresses and data.

2. 发明公开

EP0213843A2 Digital processor control 失效
标题翻译： Digitalprozessorsteuerung。
公开(公告)号：EP0213843A2
公开(公告)日：1987-03-11
申请号：EP86306268.3
申请日：1986-08-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Case, Brian , Fleck, Rod , Kong, Cheng Gang , Moller, Ole , Johnson, Michael
IPC分类号： G06F9/46 , G06F12/14
CPC分类号： G06F9/468 , G06F9/4484 , G06F9/462 , G06F12/1458
摘要： A high-speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.
摘要翻译：公开了一种适用于简化指令集计算机（RISC）的指令处理器使用的高速寄存器文件，其优选地以有效的寄存器分配方法使用。寄存器文件有助于通过动态提供两个过程可访问的重叠寄存器来在过程之间传递参数。每个过程还具有一组分配给它的“本地”寄存器，这些寄存器从其他过程无法访问。寄存器文件被分成多个块，并且保护寄存器存储一个单词，该单词通过特定的过程或任务阻止某些块的访问。以这种方式，使用寄存器文件的指令处理器可以对多个任务进行操作，保持每个任务的完整性，而不是在其他任务中发生不期望的改变。

3. 发明授权

EP0213843B1 Digital processor control 失效
标题翻译：数字处理器控制
公开(公告)号：EP0213843B1
公开(公告)日：1993-02-10
申请号：EP86306268.3
申请日：1986-08-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Case, Brian , Fleck, Rod , Kong, Cheng Gang , Moller, Ole , Johnson, Michael
IPC分类号： G06F9/46 , G06F12/14
CPC分类号： G06F9/468 , G06F9/4484 , G06F9/462 , G06F12/1458
摘要： A high-speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.

4. 发明公开

EP0180476A2 Microprogramme sequence controller 失效
标题翻译：微顺序控制器。
公开(公告)号：EP0180476A2
公开(公告)日：1986-05-07
申请号：EP85307899.6
申请日：1985-10-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Moller, Ole
IPC分类号： G06F9/26
CPC分类号： G06F9/268 , G06F13/24
摘要： A single-chip microprogram sequence controller which can be selectively operated in either an interrupt mode or a trapped mode. In the interrupt mode, the microprogram sequencer allows the currently-executing microinstruction to finish execution before beginning the interrupt routine which services the asynchronous event which requested the interruption of the presently-executing microinstruction stream. In the trap mode, the sequencer aborts the currently-executing microinstruction to avoid an irreversible error which would result if the microinstruction were to finish execution before beginning the routine which services the event which requested trapping of the presently-executing microinstruction. Depending on the mode selected, the sequencer stores the address on a last-in, first-out stack of either the next-following microinstruction or the currently-executing microinstruction for return to the proper point in the microinstruction stream upon completion of the routine which requested the interrupt or the trap.

5. 发明公开

EP0178163A2 A dual access digital storage device 失效
标题翻译：双接入数字存储设备。
公开(公告)号：EP0178163A2
公开(公告)日：1986-04-16
申请号：EP85307225.4
申请日：1985-10-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Moller, Ole , Po Loi Chu, Paul
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C8/16 , G11C7/1075
摘要： A two read-port, two write-port register file on a single integrated circuit chip provides dual read/write access via either an "A"-side or "B"-side of a single array of adressable registers. Separate on-chip "A"-side or "B"-side multiplexers permit reading or writing of an independently adressed register according to the phase of the "A"-side or "B"-side clock. Writing can be selctively effected to either a high-order and/or a low-order byte within the addressed register. Unidirectional busses connect each register to each of the four ports. The register can be expanded to provide a four read-port, two write-port register file such as is required for the parallel computation of addresses and data.

6. 发明授权

EP0180476B1 Microprogramme sequence controller 失效
标题翻译：微控制器序列控制器
公开(公告)号：EP0180476B1
公开(公告)日：1992-06-10
申请号：EP85307899.6
申请日：1985-10-31
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Moller, Ole
IPC分类号： G06F9/26
CPC分类号： G06F9/268 , G06F13/24

7. 发明公开

EP0219203A3 Computer control providing single-cycle branching 失效
标题翻译：计算机控制提供单循环分支
公开(公告)号：EP0219203A3
公开(公告)日：1989-07-19
申请号：EP86306269.1
申请日：1986-08-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Case, Brian , Fleck, Rod , Moller, Ole , Kong, Cheng-Gang
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3842
摘要： An instruction processor suitable for use in a reduced instruction-set computer employing an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutines, interrupts and traps.

8. 发明公开

EP0213842A3 Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor 失效
标题翻译：用于执行数据参考的机制与减少指令集处理器的指令执行并行存储
公开(公告)号：EP0213842A3
公开(公告)日：1989-04-26
申请号：EP86306267.5
申请日：1986-08-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Johnson, William , Fleck, Rod , Moller, Ole , Kong, Cheng-Gang
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3834
摘要： A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RiSCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data for a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the registerfile. Logic circuitry detects storage of data priorto its writing back, so as to effectively replace the register file location. During page faults, the contents of the channel address, channel data, and channel control registers are saved to permit page fault recovery.

9. 发明公开

EP0213842A2 Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor 失效
标题翻译：机构，用于并行存储器的数据收集和指令执行在处理器具有精简指令集。
公开(公告)号：EP0213842A2
公开(公告)日：1987-03-11
申请号：EP86306267.5
申请日：1986-08-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Johnson, William , Fleck, Rod , Moller, Ole , Kong, Cheng-Gang
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3834
摘要： A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RiSCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data for a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the registerfile. Logic circuitry detects storage of data priorto its writing back, so as to effectively replace the register file location. During page faults, the contents of the channel address, channel data, and channel control registers are saved to permit page fault recovery.

10. 发明授权

EP0219203B1 Computer control providing single-cycle branching 失效
标题翻译：在单周期分支计算机控制。
公开(公告)号：EP0219203B1
公开(公告)日：1995-02-15
申请号：EP86306269.1
申请日：1986-08-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Case, Brian , Fleck, Rod , Moller, Ole , Kong, Cheng-Gang
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3842

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