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1. 发明授权

EP1336198B1 METHOD OF MAKING A FUNCTIONAL DEVICE WITH DEPOSITED LAYERS SUBJECT TO HIGH TEMPERATURE ANNEAL 有权
标题翻译：一种用于生产功能设备符合下处理僻静LAYERS
公开(公告)号：EP1336198B1
公开(公告)日：2012-05-02
申请号：EP01997843.6
申请日：2001-11-22
申请人： Teledyne Dalsa Semiconductor Inc.
发明人： OUELLET, Luc , DALLAIRE, Annie
IPC分类号： G02B6/132
CPC分类号： G02B6/132 , G02B2006/12169 , Y10S438/97 , Y10S438/976
摘要： A method is disclosed for making a device having one or more deposited layers and subject to a post deposition high temperature anneal. Opposing films having similar mechanical properties are deposited on the front and back faces of a wafer, which is subsequently subjected a high temperature anneal. The opposing films tend to cancel out stress-induced warping of the wafer during the subsequent anneal.

2. 发明授权

EP0672899B1 Semiconductor pressure sensor with single-crystal silicon diaphragm and single-crystal gage elements and fabrication method therefor 失效
标题翻译：一种半导体压力传感器与单晶硅单晶膜和应变计及其制造方法
公开(公告)号：EP0672899B1
公开(公告)日：1999-10-06
申请号：EP95103971.8
申请日：1995-03-17
申请人： THE FOXBORO COMPANY
发明人： Fung, Clifford D.
IPC分类号： G01L9/06 , G01L9/00
CPC分类号： G01L9/0055 , G01L9/0042 , Y10S148/136 , Y10S438/97

3. 发明公开

EP0742584A3 High density selective SiO2:Si3N4 etching using a stoichiometrically altered nitride etch stop layer 失效
标题翻译：与SiO 2的高密度选择性蚀刻：通过氮化物的蚀刻停止层的手段的Si3N4化学计量改变
公开(公告)号：EP0742584A3
公开(公告)日：1997-10-08
申请号：EP96480038.7
申请日：1996-04-04
申请人： International Business Machines Corporation
发明人： Armacost, Michael D. , Nguyen, Son , Dobuzinsky, David , Gambino, Jeffrey
IPC分类号： H01L21/311
CPC分类号： H01L21/31105 , Y10S438/97
摘要： Selectivity of SiO 2 to Si 3 N 4 is increased with the addition of silicon rich nitride conformal layer which may be used in place of or in addition to standard nitride conformal layers in manufacture. As can be seen in the drawing, a structure having a silicon substrate (1), gate electrodes (2), nitride cap (3) and conformal nitride (4) layers is constructed. A stoichiometrically altered conformal nitride layer (6) is then added. However this structure can be constructed having the altered conformal nitride layer (6) replacing the first conformal nitride layer (4). This same type of altered nitride could additionally be included in the cap (3) of the gate electrode (2). This nitride layer consists of higher concentrations of some materials, such as silicon and hydrogen, which add substantial selectivity to the nitride film during the etch process, without substantially changing the dielectric properties of the material.

4. 发明授权

EP0368584B1 Method of manufacturing a semiconductor wafer 失效
标题翻译：的半导体晶片的制造方法
公开(公告)号：EP0368584B1
公开(公告)日：1997-03-19
申请号：EP89311454.6
申请日：1989-11-06
申请人： SONY CORPORATION
发明人： Yagi, Atsuo , Matsushita, Takeshi , Hashimoto, Makoto
IPC分类号： H01L21/76 , H01L21/78 , H01L21/84
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/31053 , H01L21/76251 , H01L21/78 , H01L29/66439 , Y10S148/012 , Y10S148/135 , Y10S438/97 , Y10S438/977

5. 发明授权

EP0511631B1 Method of manufacturing semiconductor memory 失效
标题翻译：用于半导体存储器的制造方法
公开(公告)号：EP0511631B1
公开(公告)日：1996-06-19
申请号：EP92107215.3
申请日：1992-04-28
申请人： SONY CORPORATION
发明人： Kuroda, Hideaki
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10808 , H01L27/105 , Y10S438/97

6. 发明授权

EP0455341B1 Semiconductor contact via structure and method 失效
标题翻译：半导体接触开放结构和程序
公开(公告)号：EP0455341B1
公开(公告)日：1996-05-29
申请号：EP91302577.1
申请日：1991-03-25
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Liou, Fu-Tai , Spinner, Charles Ralph
IPC分类号： H01L21/768
CPC分类号： H01L21/28512 , H01L21/7684 , H01L21/76843 , H01L21/76858 , H01L21/76877 , H01L21/76879 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S438/97 , H01L2924/00

7. 发明公开

EP0450572A3 Sealed self aligned contact process and structure 失效
标题翻译：密封自对准接触过程和结构
公开(公告)号：EP0450572A3
公开(公告)日：1994-06-01
申请号：EP91105191.0
申请日：1991-04-02
申请人： RAMTRON INTERNATIONAL CORPORATION , NMB SEMICONDUCTOR CO., LTD.
发明人： Butler, Douglas
IPC分类号： H01L21/285 , H01L21/768 , H01L29/54
CPC分类号： H01L21/76897 , H01L21/28512 , H01L21/76804 , H01L23/485 , H01L2924/0002 , Y10S438/97 , H01L2924/00
摘要： In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a TiN layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the TiN layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the TiN layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and TiN as a protective barrier; and (9) adding contact material in said windows. In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode. Titanium silicide (34) is located upon the S/D. A remnant (36a) of a (conductive) TiN layer overlies the silicide and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. A further nitride, preferably Si₃N₄, is located under the thick dielectric and over part of the gate electrode insulation. The Si₃N₄ adjoins the TiN to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by one nitride at some locations and by the other nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si₃N₄ but not the TiN. The TiN is effective as a dry etch stop and a wet etch stop, and the silicon nitride is effective as an isotropic etch stop. The conductive nitride is wholly contained within the contact, and the further nitride extends beyond said contact.
摘要翻译：在制造与集成电路的栅电极相邻的源极/漏电极的接触窗口时：（1）在栅电极旁边的源极/漏极区域上建立具有窗口的结构; （2）在源极/漏极上建立硅化钛区域，并在窗口和栅电极上建立TiN层; （3）在TiN层上建立氮化硅层; （4）构图氮化硅层; （5）使用图案化的氮化硅层作为掩模来图案化TiN层; （6）添加另一个氮化硅层以密封其不被氮化钛保护的栅电极; （7）通过各向异性蚀刻在电极上打开窗口; （8）使用氮化硅和TiN作为保护屏障，用各向同性蚀刻来加宽窗口; 和（9）在所述窗口中添加接触材料。在与栅电极（22）附近的源极/漏极区（28）的接触结构中，通过厚电介质的接触侧壁横向移位远离S / D区域以扩大触点; 接触侧壁位于栅极上方。硅化钛（34）位于S / D上。（导电）TiN层的残余物（36a）覆盖在硅化物上，沿着栅电极绝缘体的侧壁上升并且在栅电极顶部上绝缘，从而与栅电极绝缘。另外的氮化物，优选Si 3 N 4，位于厚电介质和栅电极绝缘体的一部分之下。 Si 3 N 4邻接TiN以用氮化物封闭栅电极的顶部和侧面。接触的底部由一些位置处的一个氮化物和其他位置处的另一个氮化物形成。通过厚电介质的接触侧壁优选覆盖在Si 3 N 4上而不是TiN。 TiN作为干蚀刻停止和湿蚀刻停止是有效的，并且氮化硅作为各向同性蚀刻停止是有效的。导电氮化物完全包含在触点内，并且另外的氮化物延伸超过所述触点。

8. 发明公开

EP0545263A2 Method of forming trench isolation having polishing step and method of manufacturing semiconductor device 失效
标题翻译： Verfahren zur Herstellung einer Isolationsprobe mittels einer Polierschritt。
公开(公告)号：EP0545263A2
公开(公告)日：1993-06-09
申请号：EP92120116.6
申请日：1992-11-25
申请人： SONY CORPORATION
发明人： Gocho, Tetsuo , Hayakawa, Hideaki
IPC分类号： H01L21/76 , H01L21/3105
CPC分类号： H01L21/31053 , H01L21/3065 , H01L21/31055 , H01L21/31116 , H01L21/31604 , H01L21/76229 , Y10S438/97
摘要： A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.
摘要翻译：一种形成沟槽隔离的方法，包括通过用于同时进行蚀刻和沉积的沉积装置掩埋沟槽的掩埋步骤和通过抛光来平坦化掩埋材料的抛光步骤，通过设置各向同性蚀刻步骤，多层蚀刻停止器和突起统一结构。即使在蚀刻停止层分布不均匀的部分中，也能够均匀地得到令人满意的平坦度或无抛光残渣的抛光。该方法可以应用于制造半导体器件等。

9. 发明授权

EP0338102B1 Verfahren zur Herstellung von integrierten Halbleiterstrukturen welche Feldeffekttransistoren mit Kanallängen im Submikrometerbereich enthalten 失效
标题翻译：制造具有子通道的场效应晶体管的半导体集成电路的工艺
公开(公告)号：EP0338102B1
公开(公告)日：1993-03-10
申请号：EP88106205.3
申请日：1988-04-19
申请人： International Business Machines Corporation
发明人： Koblinger, Otto, Dr. , Mühl, Reinhold , Trumpp, Hans-Joachim, Dr.
IPC分类号： H01L21/28 , H01L21/00
CPC分类号： H01L21/0271 , H01L21/28123 , Y10S148/051 , Y10S148/137 , Y10S438/947 , Y10S438/95 , Y10S438/97

10. 发明公开

EP0511631A1 Method of manufacturing semiconductor memory 失效
标题翻译： HerstellungsmethodefürHalbleiterspeicher。
公开(公告)号：EP0511631A1
公开(公告)日：1992-11-04
申请号：EP92107215.3
申请日：1992-04-28
申请人： SONY CORPORATION
发明人： Kuroda, Hideaki
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10808 , H01L27/105 , Y10S438/97
摘要： According to this invention, a conductive film (25) for forming a plate electrode of a capacitor (33) constituting a memory cell is patterned in only a memory cell region at first. After the conductive film in a peripheral circuit region is used as a stopper for wet-etching a low-melting insulating film (27) of the peripheral circuit region, the conductive film is patterned using the same mask as the low-melting insulating film or the low melting insulating film itself as a mask. For this reason, a SiN film formed by a low pressure CVD method so far used as a stopper, can be dispensed with and an additional lithographic step is not required. The memory cell region is planarized and the step of the peripheral circuit region is reduced, however, the data retaining characteristics are improved without increasing the number of steps.
摘要翻译：根据本发明，用于形成构成存储单元的电容器（33）的平板电极的导电膜（25）首先在存储单元区域中被图案化。在外围电路区域中的导电膜用作湿式蚀刻外围电路区域的低熔点绝缘膜（27）的阻挡层之后，使用与低熔点绝缘膜相同的掩模对导电膜进行图案化，或低熔点绝缘膜本身作为掩模。为此，可以省略通过目前用作止动器的低压CVD法形成的SiN膜，并且不需要附加的光刻步骤。存储单元区域被平坦化，并且外围电路区域的步骤减小，然而，在不增加步骤数量的情况下，数据保持特性得到改善。

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