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1. 发明公开

EP0469367A1 Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method 失效
标题翻译：一种用于产生用此方法自对准的，非图案化和Kontaktfläschen层电容器的方法。
公开(公告)号：EP0469367A1
公开(公告)日：1992-02-05
申请号：EP91111732.3
申请日：1991-07-15
申请人： RAMTRON INTERNATIONAL CORPORATION , NMB SEMICONDUCTOR CO., LTD.
发明人： Butler, Douglas
IPC分类号： H01L29/92 , H01L27/108
CPC分类号： H01L27/10805 , H01L28/40 , Y10S257/90
摘要： In a multilayered integrated memory circuit, a method using an insulating "sticks" is disclosed to provide a contact between two layers or regions, or one of each, where the contact does not short to an intervening conductive layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.
摘要翻译：在多层集成存储器电路，使用在绝缘性“棒”的方法是游离缺失提供两个层或区域，或每个中的一个，其中所述接触不会短路到居间导电层上的接触盘。本发明通过使用牺牲层用适当的蚀刻和蚀刻停止特性以最小的附加处理提供此。如本文层进行蚀刻，另外的层交替哪在相同的导电/绝缘图案被暴露。每个蚀刻停止在任一导电或绝缘层。然后，接触层可以被沉积于最上面的电容器板连接到所述存储单元的传输晶体管。

2. 发明公开

EP0450572A3 Sealed self aligned contact process and structure 失效
标题翻译：密封自对准接触过程和结构
公开(公告)号：EP0450572A3
公开(公告)日：1994-06-01
申请号：EP91105191.0
申请日：1991-04-02
申请人： RAMTRON INTERNATIONAL CORPORATION , NMB SEMICONDUCTOR CO., LTD.
发明人： Butler, Douglas
IPC分类号： H01L21/285 , H01L21/768 , H01L29/54
CPC分类号： H01L21/76897 , H01L21/28512 , H01L21/76804 , H01L23/485 , H01L2924/0002 , Y10S438/97 , H01L2924/00
摘要： In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a TiN layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the TiN layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the TiN layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and TiN as a protective barrier; and (9) adding contact material in said windows. In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode. Titanium silicide (34) is located upon the S/D. A remnant (36a) of a (conductive) TiN layer overlies the silicide and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. A further nitride, preferably Si₃N₄, is located under the thick dielectric and over part of the gate electrode insulation. The Si₃N₄ adjoins the TiN to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by one nitride at some locations and by the other nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si₃N₄ but not the TiN. The TiN is effective as a dry etch stop and a wet etch stop, and the silicon nitride is effective as an isotropic etch stop. The conductive nitride is wholly contained within the contact, and the further nitride extends beyond said contact.
摘要翻译：在制造与集成电路的栅电极相邻的源极/漏电极的接触窗口时：（1）在栅电极旁边的源极/漏极区域上建立具有窗口的结构; （2）在源极/漏极上建立硅化钛区域，并在窗口和栅电极上建立TiN层; （3）在TiN层上建立氮化硅层; （4）构图氮化硅层; （5）使用图案化的氮化硅层作为掩模来图案化TiN层; （6）添加另一个氮化硅层以密封其不被氮化钛保护的栅电极; （7）通过各向异性蚀刻在电极上打开窗口; （8）使用氮化硅和TiN作为保护屏障，用各向同性蚀刻来加宽窗口; 和（9）在所述窗口中添加接触材料。在与栅电极（22）附近的源极/漏极区（28）的接触结构中，通过厚电介质的接触侧壁横向移位远离S / D区域以扩大触点; 接触侧壁位于栅极上方。硅化钛（34）位于S / D上。（导电）TiN层的残余物（36a）覆盖在硅化物上，沿着栅电极绝缘体的侧壁上升并且在栅电极顶部上绝缘，从而与栅电极绝缘。另外的氮化物，优选Si 3 N 4，位于厚电介质和栅电极绝缘体的一部分之下。 Si 3 N 4邻接TiN以用氮化物封闭栅电极的顶部和侧面。接触的底部由一些位置处的一个氮化物和其他位置处的另一个氮化物形成。通过厚电介质的接触侧壁优选覆盖在Si 3 N 4上而不是TiN。 TiN作为干蚀刻停止和湿蚀刻停止是有效的，并且氮化硅作为各向同性蚀刻停止是有效的。导电氮化物完全包含在触点内，并且另外的氮化物延伸超过所述触点。

3. 发明公开

EP0450572A2 Sealed self aligned contact process and structure 失效
标题翻译： Verfahren zum Herstellen eines versiegelten selbstjustierenden Kontaktes und Struktur。
公开(公告)号：EP0450572A2
公开(公告)日：1991-10-09
申请号：EP91105191.0
申请日：1991-04-02
申请人： RAMTRON INTERNATIONAL CORPORATION , NMB SEMICONDUCTOR CO., LTD.
发明人： Butler, Douglas
IPC分类号： H01L21/285 , H01L21/768 , H01L29/54
CPC分类号： H01L21/76897 , H01L21/28512 , H01L21/76804 , H01L23/485 , H01L2924/0002 , Y10S438/97 , H01L2924/00
摘要： In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a TiN layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the TiN layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the TiN layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and TiN as a protective barrier; and (9) adding contact material in said windows.
In a contact structure to a source/drain region (28) nearby a gate electrode (22), a contact sidewall through a thick dielectric is laterally displaced away from the S/D region to widen the contact; the contact sidewall is located over the gate electrode. Titanium silicide (34) is located upon the S/D. A remnant (36a) of a (conductive) TiN layer overlies the silicide and rises up along the sidewall of gate electrode insulation and onto insulation atop the gate electrode, and is insulated from the gate electrode thereby. A further nitride, preferably Si₃N₄, is located under the thick dielectric and over part of the gate electrode insulation. The Si₃N₄ adjoins the TiN to enclose the top and sides of the gate electrode with nitride. The bottom of the contact is formed by one nitride at some locations and by the other nitride at other locations. The contact sidewall through the thick dielectric preferably overlies the Si₃N₄ but not the TiN. The TiN is effective as a dry etch stop and a wet etch stop, and the silicon nitride is effective as an isotropic etch stop. The conductive nitride is wholly contained within the contact, and the further nitride extends beyond said contact.
摘要翻译：在制造与集成电路的栅电极相邻的源极/漏电极的接触窗口时：（1）在栅电极旁边的源极/漏极区域上建立具有窗口的结构; （2）在源极/漏极上建立硅化钛区域，并在窗口和栅电极上建立TiN层; （3）在TiN层上建立氮化硅层; （4）构图氮化硅层; （5）使用图案化的氮化硅层作为掩模来图案化TiN层; （6）添加另一个氮化硅层以密封其不被氮化钛保护的栅电极; （7）通过各向异性蚀刻在电极上打开窗口; （8）使用氮化硅和TiN作为保护屏障，用各向同性蚀刻来加宽窗口; 和（9）在所述窗口中添加接触材料。在与栅电极（22）附近的源极/漏极区（28）的接触结构中，通过厚电介质的接触侧壁横向移位远离S / D区域以扩大触点; 接触侧壁位于栅极上方。硅化钛（34）位于S / D上。（导电）TiN层的残余物（36a）覆盖在硅化物上，沿着栅电极绝缘体的侧壁上升并且在栅电极顶部上绝缘，从而与栅电极绝缘。另外的氮化物，优选Si 3 N 4，位于厚电介质和栅电极绝缘体的一部分之下。 Si 3 N 4邻接TiN以用氮化物封闭栅电极的顶部和侧面。接触的底部由一些位置处的一个氮化物和其他位置处的另一个氮化物形成。通过厚电介质的接触侧壁优选覆盖在Si 3 N 4上而不是TiN。 TiN作为干蚀刻停止和湿蚀刻停止是有效的，并且氮化硅作为各向同性蚀刻停止是有效的。导电氮化物完全包含在触点内，并且另外的氮化物延伸超过所述触点。

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