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1. 发明授权

EP1355426B1 Multi-bit digital input using a single pin 有权
标题翻译：与单个连接销多位数字输入
公开(公告)号：EP1355426B1
公开(公告)日：2007-11-21
申请号：EP03008073.3
申请日：2003-04-14
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Dwelley, David M. , Reay, Robert L.
IPC分类号： H03K19/173 , H03M5/20
CPC分类号： H03K19/1732 , H04L25/49

2. 发明公开

EP1355426A1 Multi-bit digital input using a single pin 有权
标题翻译：多位数字电脑Eingang mit einem einzigen Verbindungsstift
公开(公告)号：EP1355426A1
公开(公告)日：2003-10-22
申请号：EP03008073.3
申请日：2003-04-14
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Dwelley, David M. , Reay, Robert L.
IPC分类号： H03K19/173 , H03M5/20
CPC分类号： H03K19/1732 , H04L25/49
摘要： Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.
摘要翻译：用于通过单个引脚传输，传送和/或传送多位数字信号作为电压信号的电子设备和方法。根据本发明的装置和方法基本上减少了装置的引脚数，因为多位数字信号的输入优选地不使用多于一个的输入引脚。此外，与串行相反，多位数字信号基本上一次作为电压信号发送，从而提高了传输速度。

3. 发明公开

EP0600488A3 Lead frame capacitor and capacitively-coupled isolator circuit using same 失效
标题翻译： Leiterrahmen-Kondensator und Kapazitiv gekoppelten Trennschaltung damit。
公开(公告)号：EP0600488A3
公开(公告)日：1995-02-01
申请号：EP93119453.4
申请日：1993-12-02
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Dobkin, Robert C. , Reay, Robert L.
IPC分类号： H01L23/64 , H01L23/495 , H03K5/24
CPC分类号： H01L23/49575 , H01L23/49589 , H01L23/642 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K1/162 , H05K3/202 , Y10S257/904 , Y10T29/435 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： A capacitor (10) is provided including first and second electrodes (12,14) formed from portions of the lead frame structure (30) used in conventional integrated circuit packaging. The electrodes (12,14) are encapsulated with dielectric molding material (40) which provides dielectric insulation between the electrodes (12,14). A low power capacitively-coupled digital isolator circuit (50) is also provided. The circuit employs a pair of the lead frame capacitors (105,115) of the present invention and includes differential driver and receiver circuits (110,120). The receiver (120) can also include an optional filter (136) for increasing noise and glitch immunity.
摘要翻译：提供一种电容器（10），包括由常规集成电路封装中使用的引线框架结构（30）的部分形成的第一和第二电极（12,14）。电极（12,14）用介电模塑材料（40）封装，其在电极（12,14）之间提供绝缘绝缘。还提供了一种低功率电容耦合数字隔离电路（50）。该电路采用本发明的一对引线框电容器（105,115），并包括差分驱动器和接收器电路（110,120）。接收器（120）还可以包括用于增加噪声和毛刺抗扰度的可选滤波器（136）。

4. 发明授权

EP2056208B1 Circuits and methods for interconnecting bus systems 失效转让
标题翻译：电路和方法的总线系统彼此连接
公开(公告)号：EP2056208B1
公开(公告)日：2014-04-23
申请号：EP09150579.2
申请日：2001-12-11
申请人： Linear Technology Corporation
发明人： Reay, Robert L. , Ziegler, John H.
IPC分类号： G06F13/40
CPC分类号： G06F13/4081

5. 发明公开

EP2056209A1 Circuits and methods for interconnecting bus systems 失效转让
标题翻译：连接总线系统的电路和方法
公开(公告)号：EP2056209A1
公开(公告)日：2009-05-06
申请号：EP09150580.0
申请日：2001-12-11
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Reay, Robert L. , Ziegler, John H.
IPC分类号： G06F13/40
CPC分类号： G06F13/4081
摘要： Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a "hot-swappable" fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card ( Fig. 1 ).
摘要翻译：提供了用于互连带电背板和至少一个I / O卡的电路和方法。本发明提供了互连电路，其利用缓冲电路以“热插拔”方式将底板的数据和时钟总线连接到I / O卡的数据和时钟总线。缓冲电路还将与背板相关的电容与I / O卡相关的电容隔离开来。例如，当至少一个信号从背板驱动到I / O卡时，该信号只需要克服与背板相关联的电容。相反，当至少有一个信号从I / O卡驱动到背板时，该信号只需要克服与I / O卡相关的电容。因此，这种电容隔离便于背板和I / O卡之间的信号传输（图1）。

6. 发明授权

EP1213655B1 Circuits and methods for interconnecting bus systems 失效转让
标题翻译：电路和方法，用于总线系统的连接
公开(公告)号：EP1213655B1
公开(公告)日：2011-08-24
申请号：EP01129255.4
申请日：2001-12-11
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Reay, Robert L. , Ziegler, John H.
IPC分类号： G06F13/40
CPC分类号： G06F13/4081

7. 发明公开

EP2060978A1 Circuits and methods for interconnecting bus systems 有权转让
标题翻译： Schaltkreise und Verfahren zum Verbinden von Bussystemen miteinander
公开(公告)号：EP2060978A1
公开(公告)日：2009-05-20
申请号：EP09150581.8
申请日：2001-12-11
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Reay, Robert L. , Ziegler, John H.
IPC分类号： G06F13/40
CPC分类号： G06F13/4081
摘要： Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a "hot-swappable" fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card ( Fig. 1 ).
摘要翻译：提供了用于互连活动背板和至少一个I / O卡的电路和方法。本发明提供了利用缓冲电路将背板的数据和时钟总线以“热插拔”方式连接到I / O卡的数据和时钟总线的互连电路。缓冲电路还将与背板相关的电容与I / O卡相关的电容隔离开来。例如，当至少一个信号从背板驱动到I / O卡时，该信号仅需克服与背板相关联的电容。相反，当至少一个信号从I / O卡驱动到背板时，信号只需要克服与I / O卡相关的电容。因此，这种电容隔离有利于背板和I / O卡之间的信号传播（图1）。

8. 发明公开

EP1608070A2 Multi-bit digital input using a single pin 有权
标题翻译：多位数字电脑Eingang mit einem einzigen Verbindungsstift
公开(公告)号：EP1608070A2
公开(公告)日：2005-12-21
申请号：EP05018493.6
申请日：2003-04-14
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Dwelley, David M. , Reay, Robert L.
IPC分类号： H03K19/173 , H03M5/20
CPC分类号： H03K19/1732 , H04L25/49
摘要： Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.
摘要翻译：用于通过单个引脚传输，传送和/或传送多位数字信号作为电压信号的电子设备和方法。根据本发明的装置和方法基本上减少了装置的引脚数，因为多位数字信号的输入优选地不使用多于一个的输入引脚。此外，与串行相反，多位数字信号基本上一次作为电压信号发送，从而提高了传输速度。

9. 发明授权

EP2060978B1 Circuits and methods for interconnecting bus systems 有权转让
标题翻译：连接总线系统的电路和方法
公开(公告)号：EP2060978B1
公开(公告)日：2013-02-13
申请号：EP09150581.8
申请日：2001-12-11
申请人： Linear Technology Corporation
发明人： Reay, Robert L. , Ziegler, John H.
IPC分类号： G06F13/40
CPC分类号： G06F13/4081

10. 发明公开

EP1213655A3 Circuits and methods for interconnecting bus systems 失效转让
标题翻译：电路和方法，用于总线系统的连接
公开(公告)号：EP1213655A3
公开(公告)日：2003-03-26
申请号：EP01129255.4
申请日：2001-12-11
申请人： LINEAR TECHNOLOGY CORPORATION
发明人： Reay, Robert L. , Ziegler, John H.
IPC分类号： G06F13/40
CPC分类号： G06F13/4081
摘要： Circuits and methods for interconnecting a live backplane and at least one I/O card are provided. This invention provides interconnection circuitry that utilizes buffer circuitry to connect the data and clock busses of the backplane to the data and clock busses of the I/O card in a "hot-swappable" fashion. Buffer circuitry also isolates the capacitance associated with the backplane from the capacitance associated with the I/O card. For example, when at least one signal is driven from the backplane to the I/O card, the signal need only overcome the capacitance associate with the backplane. Conversely, when at least one signal is driven from the I/O card to the backplane, the signal need only overcome the capacitance associated with the I/O card. Hence, this capacitive isolation facilitates signal propagation between the backplane and the I/O card (Fig. 1).

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