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1. 发明公开

EP3238390A4 COMBINED GUARANTEED THROUGHPUT AND BEST EFFORT NETWORK-ON-CHIP 有权
公开(公告)号：EP3238390A4
公开(公告)日：2018-07-18
申请号：EP15873990
申请日：2015-11-24
申请人： INTEL CORP
发明人： CHEN GREGORY K , ANDERS MARK A , KAUL HIMANSHU , KRISHNAMURTHY RAM K , STILLMAKER AARON T
IPC分类号： H04L12/771 , G06F13/14 , G06F15/78 , H04L12/64 , H04L12/863 , H04L12/911 , H04L12/931 , H04L12/935
CPC分类号： H04L47/625 , G06F15/7825 , H04L12/6402 , H04L47/72 , H04L49/30
摘要： A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

2. 发明公开

EP3014818A4 A METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) 审中-公开
标题翻译：方法，装置和系统源同步线路交换网络芯片（NOC）
公开(公告)号：EP3014818A4
公开(公告)日：2017-03-15
申请号：EP13888327
申请日：2013-06-28
申请人： INTEL CORP
发明人： CHEN GREGORY K , ANDERS MARK A , KAUL HIMANSHU , SATPATHY SUDHIR K , KRISHNAMURTHY RAM K
IPC分类号： H04L12/50 , G06F15/78
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/7825 , H04L12/46 , H04L49/109 , H04L67/10 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
摘要翻译：，实施例中的路由器包括多个输入端口和输出端口，其中，所述路由器是源同步混合网络上芯片（NOC），以使基于在路由器之间传送的控制流信号转变NOC的路由器之间的通信。其他实施例中描述并要求保护。

3. 发明公开

EP1135856A4 SINGLE ENDED INTERCONNECT SYSTEMS 审中-公开
标题翻译：非对称链路系统
公开(公告)号：EP1135856A4
公开(公告)日：2003-05-21
申请号：EP99951415
申请日：1999-09-10
申请人： INTEL CORP
发明人： KRISHNAMURTHY RAM K , SOUMYANATH KRISHNAMURTHY
IPC分类号： H04L25/02 , H03K3/12 , H03K3/286
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： In some embodiments, the invention includes an interconnect system (50) having a single ended driver (54) and single ended hysteretic receiver (58). A single ended interconnect (66) is coupled between the single ended driver and single ended receiver. In other embodiments (figure 4), the invention involves an interconnect system including interconnects (66A, 66B), single ended drivers (54A, 54B), and single ended hysteretic receivers (58A, 58B) connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals (Din(0), Din(1)) and an enable signal (Enable) and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted. In yet other embodiments (140), the invention includes an interconnect system having interconnects (66A, 66B), quasi-static drivers (142A, 142B) and receivers (150A, 150B) connected to respective ones of the interconnects, the quasi-static drivers receive a clock signal (CLK) and respective data-in signals (Din(0), Din(1)), and wherein the interconnect signals are pre-discharged when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals. In still other embodiments, the invention includes a pseudo differential interconnect system (90) and an interconnect system with a dual rail driver (190).

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