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1. 发明公开

EP3001570A1 METHOD FOR REALIZING TURBO EQUALIZATION COMPENSATION, AND TURBO EQUALIZER AND SYSTEM 有权转让
标题翻译： VERFAHREN ZURDURCHFÜHRUNGVON TURBOENTZERRUNGSKOMPENSATION SOWIE TURBOENTZERRER UND SYSTEM
公开(公告)号：EP3001570A1
公开(公告)日：2016-03-30
申请号：EP13888637.9
申请日：2013-07-01
申请人： Huawei Technologies Co., Ltd.
发明人： CHANG, Deyuan , XIAO, Zhiyu , YU, Fan , ZHAO, Yu
IPC分类号： H03M13/03
CPC分类号： H03M13/1154 , H03M13/2957 , H03M13/2987 , H03M13/3746 , H03M13/3972 , H03M13/616 , H03M13/6331 , H03M13/6561 , H04B10/25073 , H04B10/2543 , H04B10/2569 , H04B10/6161 , H04B10/6162 , H04L1/0045 , H04L1/0057 , H04L25/0202 , H04L25/03057 , H04L25/03171 , H04L2025/03789
摘要： Embodiments of the present invention relate to a method for implementing Turbo equalization compensation, an equalizer, and a system. The method for implementing Turbo equalization compensation includes: dividing a first data block into n data segments, where D bits in two adjacent data segments in the n data segments overlap, performing recursive processing on each data segment in the n data segments, and merging the n data segments on which the recursive processing has been performed, to obtain a second data block; and performing iterative decoding on the second data block, to output a third data block, where data lengths of the first data block, the second data block, and the third data block are all 1/T of a code length of a LDPC convolutional code. The embodiments of the present invention are applied to a receive end of a high-speed optical fiber transmission system. By performing, in an OP-BCJR unit, segmentation processing and forward and backward recursive operations on a received data block, and performing, in an LDPC convolutional code decoding unit, Turbo iterative processing on data obtained from the OP-BCJR unit, a system throughput can be effectively improved.
摘要翻译：本发明的实施例涉及一种用于实现Turbo均衡补偿，均衡器和系统的方法。用于实现Turbo均衡补偿的方法包括：将第一数据块划分为n个数据段，其中n个数据段中的两个相邻数据段中的D位重叠，对n个数据段中的每个数据段执行递归处理，并合并在其上执行了递归处理的n个数据段，以获得第二数据块; 并对第二数据块执行迭代解码，以输出第三数据块，其中第一数据块，第二数据块和第三数据块的数据长度都是LDPC卷积码的码长的1 / T 。本发明的实施例应用于高速光纤传输系统的接收端。通过在OP-BCJR单元中执行对接收数据块的分段处理和向前和向后递归运算，并且在LDPC卷积码解码单元中对从OP-BCJR单元获得的数据进行Turbo迭代处理，吞吐量可以有效提高。

2. 发明公开

EP2520026A1 ITERATIVE DECODING AND DEMODULATION WITH FEEDBACK ATTENUATION 有权
标题翻译：迭代解码和解调具有反馈的弱化
公开(公告)号：EP2520026A1
公开(公告)日：2012-11-07
申请号：EP10810982.8
申请日：2010-12-15
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： KHAYRALLAH, Ali, S. , BOTTOMLEY, Gregory, E. , CHENG, Jung-Fu
IPC分类号： H03M13/29 , H03M13/37
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/296 , H03M13/3707 , H03M13/6325 , H03M13/6561 , H03M13/658 , H03M13/6591 , H04L1/005 , H04L25/03286
摘要： An iterative demodulator and decoder uses feedback attenuation to maintain proper balance between the demodulator and decoder. Balance is maintained by attenuating the influence of extrinsic information fed back from the decoder to the demodulator to prevent strong decisions by the decoder from overwhelming the demodulator.

3. 发明授权

EP1030457B1 Methods and system architectures for turbo decoding 有权
标题翻译：对turbo解码的方法和系统的体系结构
公开(公告)号：EP1030457B1
公开(公告)日：2012-08-08
申请号：EP00200557.7
申请日：2000-02-18
申请人： IMEC
发明人： Giese, Jochen Uwe , Schurgers, Curt , Van der Perre, Liesbet , Gyselinckx, Bert , Catthoor, Francky , Engels, Marc
IPC分类号： H03M13/29 , H03M13/39 , H03M13/45
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/2987 , H03M13/3723 , H03M13/3922 , H03M13/3972

4. 发明公开

EP2005597A1 SCHEDULING PIPELINED STATE UPDATE FOR HIGH-SPEED TRELLIS PROCESSING 审中-公开
标题翻译：管道状态更新对高-SPEED TRELLIS处理协调
公开(公告)号：EP2005597A1
公开(公告)日：2008-12-24
申请号：EP07759300.2
申请日：2007-03-23
申请人： TRELLISWARE TECHNOLOGIES, INC.
发明人： DIMOU, Georgios, D.
IPC分类号： H03M13/41 , H03M13/39 , H04L1/00
CPC分类号： H03M13/4107 , H03M13/03 , H03M13/2987 , H03M13/3905 , H03M13/3922 , H03M13/41 , H03M13/6502
摘要： Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.

5. 发明公开

EP1315299A4 INTERLEAVING APPARATUS 审中-公开
标题翻译：交错
公开(公告)号：EP1315299A4
公开(公告)日：2006-12-27
申请号：EP01961288
申请日：2001-08-31
申请人： SONY CORP
发明人： YOKOKAWA TAKASHI , MIYAUCHI TOSHIYUKI , YAMAMOTO KOUHEI
IPC分类号： G06F11/10 , H03M13/27 , H03M13/29 , H03M13/39 , H03M13/41 , H03M13/45 , H04L1/00
CPC分类号： H03M13/2767 , H03M13/235 , H03M13/2771 , H03M13/2903 , H03M13/2987 , H03M13/3911 , H03M13/3927 , H03M13/3988 , H03M13/41 , H03M13/6516 , H03M13/6566 , H03M13/6572 , H04L1/0043 , H04L1/0052 , H04L1/0055 , H04L1/0059 , H04L1/0066 , H04L1/0071
摘要： Interleave of plural types are realized, and decoding adaptively corresponding to codes of various types is conducted through a simple constitution. An interleaver (100) of an element decoder has a plurality of storage circuits (407) where data is stored, a control circuit (400) for generating address data for writing data in the storage circuits (407) and address data for reading the data from the storage circuits (407), an address selecting circuit (405) for selecting address data to be distributed to the storage circuits (407) in accordance with the mode indicating the structure of codes including the type of interleave to be conducted, an input data selecting circuit (406) for selecting data to be distributed to the storage circuits (407) in accordance with the mode, and an output data selecting circuit (408) for selecting data to be outputted in accordance with the mode. A storage circuit to be used is selected from among the storage circuits (407).

6. 发明公开

EP1153482A1 INTERLEAVER DESIGN FOR PARSED PARALLEL CONCATENATED CODES 审中-公开
标题翻译：全面建设交织分布式并行套接码
公开(公告)号：EP1153482A1
公开(公告)日：2001-11-14
申请号：EP00986505.6
申请日：2000-12-14
申请人： Hughes Electronics Corporation
发明人： ELGAMAL, Hesham, M. , HAMMONS, Roger, A., Jr. , EROZ, Mustafa
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H04L1/0041 , H03M13/2746 , H03M13/2771 , H03M13/296 , H03M13/2987 , H03M13/6362 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method and apparatus for interleaving an input data stream for parsed parallel concatenated code encoding, the method comprising the steps of: parsing the input data stream into a plurality of parsed data substreams; and forming sets of shared information bits, wherein each of the sets of shared information bits comprises information bits in common with respective pairs of the plurality of parsed data substreams. In a variation, a further step comprises constructing constituent permutations of one or more of the sets of shared information bits. In yet a further variation, a further step comprises interlacing respective pairs of the sets of shared information bits to form respective interleaved data substreams.

7. 发明授权

EP3001585B1 OPTICAL COHERENT RECEIVER WITH FORWARD ERROR CORRECTION AND PARALLEL DECODING 有权转让
标题翻译：具有前向纠错和并行译码的光学相干接收机
公开(公告)号：EP3001585B1
公开(公告)日：2017-07-12
申请号：EP14306516.7
申请日：2014-09-29
申请人： ALCATEL LUCENT
发明人： Razzetti, Luca , Gavioli, Giancarlo , Pepe, Marianna , Costantini, Carlo
IPC分类号： H03M13/29 , H04L1/00 , H04B10/61 , H03M13/00 , H03M13/11 , H03M13/37
CPC分类号： H04L1/005 , H03M13/1111 , H03M13/1145 , H03M13/2963 , H03M13/2987 , H03M13/3746 , H03M13/6561 , H04B10/616 , H04L1/0057

8. 发明公开

EP1836771A1 COMBINED-REPLICA GROUP-SHUFFLED ITERATIVE DECODER, AND METHOD FOR GENERATING THE SAME 审中-公开
标题翻译：迭代集团分配的组合副本解码器及其制造方法
公开(公告)号：EP1836771A1
公开(公告)日：2007-09-26
申请号：EP06702490.1
申请日：2006-01-06
申请人： MITSUBISHI ELECTRIC CORPORATION , UNIVERSITY OF HAWAII
发明人： YEDIDIA, Jonathan, S. , FOSSORIER, Marc P. C. , ZHANG, Juntan , WANG, Yige
IPC分类号： H03M13/29 , H03M13/11
CPC分类号： H03M13/2987 , H03M13/1108 , H03M13/1111 , H03M13/114 , H03M13/1194 , H03M13/6561
摘要： A method generates a combined-replica group-shuffled iterative decoder. First, an error-correcting code and an iterative decoder for an error-correcting code is received. Multiple group-shuffled sub-decoders for the error-correcting code are constructed, based on the iterative decoder. Then, the multiple group-shuffled sub-decoders are combined into a combined-replica group-shuffled iterative decoder. The new combined iterative decoder is applicable for LDPC codes as well as turbo and torbo product codes.

9. 发明公开

EP1024601A1 Pipelined architecture to decode parallel and serial concatenated codes (turbo codes) 审中-公开
标题翻译：管道建筑工程技术规范（涡轮编码）
公开(公告)号：EP1024601A1
公开(公告)日：2000-08-02
申请号：EP00101241.8
申请日：2000-01-25
申请人： TRW Inc.
发明人： Smith, Ronald P. , Saunders, Oliver W.
IPC分类号： H03M13/29
CPC分类号： H03M13/2987 , H03M13/2957
摘要： The present invention provides a method and apparatus (400) for iteratively decoding data which has been encoded with contatenated codes. The apparatus (400) includes pipelined and cascaded decoder processors (406, 430 and 436) connected to a multiple block memory device (402), through a multiplexing and data control block (404). A data decision element (437) is provided for generating decoded output data. The method includes receiving encoded data (802) while data already received is processed iteratively by decoder processors in a pipelined fashion. Decoder processors are designated to perform particular iterations (810) of an iterative decoding process which are performed simultaneously. As a decoder processor completes processing its designated iteration on a block of data, the decoder processor outputs decoding information (808) to the decoding processor designated to perform the subsequent iteration. Upon completion of all iterations for a block of data, the method includes generating output (814) consisting of the decoded data block. The method provides that once processing is complete on a data block, the memory block is made available (816) for the storing of new encoded input data.
摘要翻译：本发明提供了一种迭代地解码已经用连续编码编码的数据的方法和装置（400）。装置（400）包括通过复用和数据控制块（404）连接到多块存储器装置（402）的流水线化和级联解码器处理器（406,430和436）。提供用于产生解码输出数据的数据判定元件（437）。该方法包括接收编码数据（802），而已经接收的数据被解码器处理器以流水线方式迭代地处理。指定解码器处理器执行同时执行的迭代解码处理的特定迭代（810）。当解码器处理器完成对数据块处理其指定的迭代时，解码器处理器将解码信息（808）输出到被指定进行后续迭代的解码处理器。在完成数据块的所有迭代之后，该方法包括生成由解码的数据块组成的输出（814）。该方法提供一旦处理在数据块上完成，存储块就可用于存储新的编码输入数据（816）。

10. 发明授权

EP0511141B1 Procédé de codage correcteur d'erreurs à au moins deux codages convolutifs systématiques en parallèle, procédé de décodage itératif, module de décodage et décodeur correspondants 失效
标题翻译：纠错编码方法的相似之处具有至少两个系统的Faltungsenkodern，迭代解码方法，用于解码模块和解码器
公开(公告)号：EP0511141B1
公开(公告)日：1996-12-11
申请号：EP92460013.3
申请日：1992-04-22
申请人： FRANCE TELECOM , TELEDIFFUSION DE FRANCE SA
发明人： Berrou, Claude
IPC分类号： H03M13/12 , H03M13/22
CPC分类号： H04L1/0066 , H03M13/23 , H03M13/27 , H03M13/2957 , H03M13/2987 , H03M13/39 , H03M13/6362 , H03M13/658 , H04L1/005 , H04L1/0068 , H04L1/0071

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