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1. 发明授权

EP2413504B1 Clock generating apparatus with an apparatus for calibrating timing mismatch of edge rotator operating on multiple phases of oscillator 有权
标题翻译：具有用于校准Kantenrotators的时间失配，其在多个振荡器级的操作的装置，时钟发生装置
公开(公告)号：EP2413504B1
公开(公告)日：2017-01-11
申请号：EP11005949.0
申请日：2011-07-20
申请人： MediaTek Inc.
发明人： Wang, Chi-Hsueh , Staszewski, Robert Bogdan
IPC分类号： H03L7/099 , H03K5/00
CPC分类号： H03L7/0996

2. 发明公开

EP2437395A1 REFERENCE FREQUENCY GENERATOR DEVICE 审中-公开
标题翻译：参考频率发生器装置
公开(公告)号：EP2437395A1
公开(公告)日：2012-04-04
申请号：EP10780376.9
申请日：2010-04-15
申请人： Furuno Electric Co., Ltd.
发明人： MIYAHARA, Kazunori
IPC分类号： H03L7/14 , H03L7/085
CPC分类号： H03L7/14 , H03L7/0996 , H03L2207/50
摘要： The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitally controlled oscillator (26) based on a synchronizing control signal acquired based on a reference signal from the GPS receiver (21). The memory unit (29) stores a correspondence relation between a control value of the synchronizing control signal, and a voltage value and a temperature at that time. When the reference signal is not acquired, the controller 22 determines a holdover control signal based on the correspondence relation, and the voltage and temperature detected by the detector 28, and controls the digitally controlled oscillator (26).
摘要翻译：所公开的是包括GPS接收器（21），PLL电路（31），检测器（28），存储器单元（29）和控制器（22）的参考频率产生装置（11）。 PLL电路（31）基于基于来自GPS接收器（21）的参考信号获取的同步控制信号来控制数字控制振荡器（26）。存储单元（29）存储同步控制信号的控制值与此时的电压值和温度之间的对应关系。当未获取参考信号时，控制器22基于对应关系以及由检测器28检测到的电压和温度来确定保持控制信号，并控制数字控制振荡器（26）。

3. 发明公开

EP2191573A1 SPREAD SPECTRUM CLOCKING IN FRACTIONAL-N PLL 有权
标题翻译：在分数N分频PLL扩频时序
公开(公告)号：EP2191573A1
公开(公告)日：2010-06-02
申请号：EP08803731.2
申请日：2008-09-05
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： SAREEN, Puneet , SEIBOLD, Hermann
IPC分类号： H03L7/099 , H03L7/197
CPC分类号： H03L7/0998 , H03L7/0996 , H03L7/18
摘要： A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase- frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal. A logic interface circuit combines the directional control output signal from the spread spectrum logic circuitry, the phase step control signal from the spread spectrum logic circuitry, and the phase step control signal from the fractional logic circuitry. This means that when both of the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in thesame direction, a single phase step control signal is passed to the phase selector and a further phase step control signal is passed to the phase selector in a subsequent clock period. Further, when the spread spectrum logic circuitry and the fractional logic circuitry request a phase step in the same feedback clock period in opposite directions, no phase step control signal is passed to the phase selector.

4. 发明授权

EP1336270B1 AN ARRANGEMENT FOR CAPTURING DATA 有权
标题翻译：安排数据的获取
公开(公告)号：EP1336270B1
公开(公告)日：2007-01-24
申请号：EP01970444.4
申请日：2001-09-24
申请人： Infineon Technologies AG
发明人： FYVIE, Clifford, D.
IPC分类号： H04L7/033 , G06F1/00
CPC分类号： H03L7/07 , H03L7/081 , H03L7/0996 , H03L7/18 , H04L7/0337
摘要： An arrangement for capturing data from a data stream of a predetermined data transfer rate by means of a flip-flop (I2), comprises a symmetrical multi-phase clock generator (I3) that is adapted to be locked to a reference clock which in turn is adapted to generate a reference clock signal at the data transfer rate or at a fraction thereof, the multi-phase clock generator (I3) being adapted to generate n clock signals mutually shifted 360 °/n from each other, and a selector (I7) that is conneced to the clock generator (I3) to receive the n clock signals, the selector (I7) being adapted to select one of these n clock signals as the system clock signal in response to a control signal from a clock phase counter (I8), the clock phase counter (I8) being controlled to count up or down in response to the phase of the system clock signal when a predetermined number of data transitions have occurred in the data stream, said flip-flop (I2) being adapted to be controlled by the opposite phase of the system clock signal to capture said data from the data stream.

5. 发明公开

EP1624574A1 Digital spread spectrum clock signal generation 审中-公开
标题翻译：数字扩频时钟信号的产生
公开(公告)号：EP1624574A1
公开(公告)日：2006-02-08
申请号：EP05107261.9
申请日：2005-08-05
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Seibold, Hermann , Rombach, Gerd
IPC分类号： H03L7/099 , H03L7/081 , H03L7/12 , H04B1/707
CPC分类号： H03L7/0996 , H03L7/081 , H03L7/0998 , H04B2215/067
摘要： To generate a spread frequency spectrum clock signal in a digital approach permitting to make the key parameters independent of process, temperature and supply voltage variations, a digital phase locked loop is used. In a first step (a), a clock signal at a maximum clock frequency (fmax) is generated. In a second step (b), the clock frequency is stepwise reduced by incrementally adding phase delay steps to the clock signal until a minimum clock frequency (fmin) is reached. In a further step (c), the number of incrementally added phase delay steps is stepwise reduced until the maximum clock frequency (fmax) is reached. Steps (a) to (c) are continuously repeated.
摘要翻译：为了以数字方式产生扩频频谱时钟信号，允许独立于过程，温度和电源电压变化而形成关键参数，使用数字锁相环。在第一步骤（a）中，产生最大时钟频率（fmax）的时钟信号。在第二步骤（b）中，通过向时钟信号递增地增加相位延迟步骤来逐步降低时钟频率，直到达到最小时钟频率（fmin）。在进一步的步骤（c）中，递增地增加的相位延迟步骤的数量逐步减小，直到达到最大时钟频率（fmax）。步骤（a）至（c）连续重复。

6. 发明公开

EP1422826A1 Exact self-calibration of a pll with multiphase clocks 有权
标题翻译： Genaue Selbstkalibrierung einer einen mehrphasigen Takt erzeugenden Phasenregelschleife
公开(公告)号：EP1422826A1
公开(公告)日：2004-05-26
申请号：EP02447227.6
申请日：2002-11-21
申请人： STMicroelectronics Belgium N.V.
发明人： Craninckx, Jan Frans Lucien
IPC分类号： H03L7/18 , H03L7/099 , H03L7/089
CPC分类号： H03L7/0996 , H03L7/081 , H03L7/0891 , H03L7/18
摘要： The present invention is related to a Phase-Locked Loop with multiphase clocks with

a first loop (Main loop) comprising, coupled in cascade, a Phase Frequency Detector (PFD) (1), a Main Charge Pump (2), a Main Loop Filter (3), a Multi-Phase Voltage Controlled Oscillator (VCO) (4) and a Phase-switching Fractional Divider (5), and
a second loop (for Calibration) comprising the series connection of a Multiplexer (6) and Y Calibration Loop Filters (7), with Y being an integer, coupled between said Phase Frequency Detector (PFD) (1) and said Multi-Phase Voltage Controlled Oscillator (VCO) (4), said Multiplexer (6) being controlled by a Control Logic (8) coupled to said Phase-Switching Fractional Divider (5), and a Reference Frequency Signal (9) being applied to said Phase Frequency Detector (PFD) (1),
characterised in that said Multiplexer (6) has an input connected to an output of said Main Charge Pump (2), and has outputs connected to inputs of said Main Loop Filter (3) and of said Y Calibration Loop Filters (7),
and in that a Calibration signal (11) is applied at a control input of said Control Logic (8).
摘要翻译：本发明涉及具有多相时钟的锁相环，具有第一回路（主回路），其包括级联耦合的相位检波器（PFD）（1），主电荷泵（2），主回路滤波器（3），多相电压控制振荡器（VCO）（4）和相位切换分数分频器（5），以及第二回路（用于校准），包括多路复用器（6）和Y校准环路滤波器（7），其中Y是整数，耦合在所述相位频率检测器（PFD）（1）和所述多相压控振荡器（VCO）（4）之间，所述多路复用器（6）由控制逻辑（8）耦合到所述相位切换分数分频器（5），以及参考频率信号（9），其被施加到所述相位频率检测器（PFD）（1），其特征在于，所述多路复用器（6）具有连接到所述主电荷泵（2）的输出，并且具有连接到所述主回路滤波器（3）和所述Y卡利（7），并且在所述控制逻辑（8）的控制输入处施加校准信号（11）。

7. 发明公开

EP1351390A1 Low jitter phase rotator 审中-公开
标题翻译： Phasendreher mit geringem Zittern
公开(公告)号：EP1351390A1
公开(公告)日：2003-10-08
申请号：EP03007417.3
申请日：2003-04-01
申请人： Broadcom Corporation
发明人： Chen, Chun Ying
IPC分类号： H03K5/13 , H03L7/081 , H04L7/033 , H03H11/16
CPC分类号： H03L7/0996 , G11B20/1403 , H03L7/0891 , H03L7/18
摘要： A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers (812) configured to receive a plurality of input differential signals (250) having different phases, and configured to generate a plurality of weighted signals (815) responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups (811), each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a k th phase, N/4 adjacent DACs are activated that are indexed as m 0 , m 1, ...m ((N/4)-1) , wherein N is the number of said plurality of DACs. At (k+1) th phase, a m (N/4) DAC is activated that is adjacent to the m ((N/4)-1) DAC. At (k+2) th phase, the m 0 DAC is de-activated.
摘要翻译：相位旋转器产生具有多个具有减小的相位抖动的可能输出相位的输出信号。低抖动相位旋转器包括多个差分放大器（812），其被配置为接收具有不同相位的多个输入差分信号（250），并且被配置为响应于多个输入差分信号产生多个加权信号（815）。多个数模转换器（DAC）被布置成多个组（811），每组DAC被配置为为相应的差分放大器之一提供电流。每组DAC中的有源DAC的数量确定加权信号的相对加权，其中相对加权确定相位旋转器的输出信号的输出相位。 DAC配置为调整相位旋转器的输出相位。在第k阶段，N / 4相邻的DAC被激活，其被索引为m0，m1，... m（（N / 4）-1），其中N是所述多个DAC的数量。在（k + 1）相位，与m（（N / 4）-1）DAC相邻的m（N / 4）DAC被激活。在（k + 2）阶段，m0 DAC被去激活。

8. 发明授权

EP0929940B1 FREQUENCY SYNTHESIZER HAVING PHASE ERROR FEEDBACK FOR WAVEFORM SELECTION 失效
标题翻译：频率合成相位误差反馈波形选择
公开(公告)号：EP0929940B1
公开(公告)日：2002-12-18
申请号：EP97945443.6
申请日：1997-10-07
申请人： Sarnoff Corporation
发明人： SAUER, Donald, T.
IPC分类号： H03L7/06 , H03L7/099 , H03L7/16 , H03L7/081
CPC分类号： H03L7/081 , H03L7/0996 , H03L7/16

9. 发明公开

EP1199837A2 Sampling clock generation circuit, data transfer control device, and electronic equipment 有权
标题翻译：电路，用于产生用于数据传送装置的采样时钟;和电子设备
公开(公告)号：EP1199837A2
公开(公告)日：2002-04-24
申请号：EP01124703.8
申请日：2001-10-16
申请人： SEIKO EPSON CORPORATION
发明人： Kamihara, Yoshiyuki
IPC分类号： H04L7/033 , G06F13/38
CPC分类号： G06F1/06 , H03K3/0322 , H03L7/0996 , H03L7/18 , H04L7/0337
摘要： A sampling clock generation circuit and a data transfer control device make it possible to ensure a set-up time and the like during sampling, while maintaining a high frequency. A sampling clock generation circuit comprises an edge detection circuit detecting between which two edges an edge of data DIN (data to be transferred in USB 2.0 HS mode) is located, the two edges are among edges of clocks CLK0 to CLK4 that have the same frequency but mutually different phases, and a clock selection circuit, which selects one of CLK0 to CLK4 based on this edge detection information and outputs the thus-selected clock as a sampling clock SCLK. When the set-up time of a D flip-flop of the edge detection circuit is TS, the hold time is TH, and the period of the clock is T, N which is the number of a multi-phase clock is given by: N ≦ [T/(TS + TH)] (where [X] is the maximum integer that does not exceed X). The clock that has an edge that is shifted by a set number M from an edge of the data DIN is selected as SCLK.
摘要翻译：采样时钟生成电路和数据传输控制装置使得能够确保一组时间和采样期间等，同时维持高的频率。采样时钟生成电路在数据DIN的边缘两个边缘之间检测边沿检测电路的方法包括：（数据以USB要传输2.0 HS模式）的位置，所述两个边缘到CLK4时钟CLK0的边缘中thathave相同的频率但相互不同的相位，和时钟选择电路，其选择基于该边缘检测信息到CLK4 CLK0的一个和所选择的时钟由此作为一种采样时钟SCLK输出。当边缘检测电路的D触发器的设置时间是TS，保持时间是TH，并且时钟的周期是T，N的所有这是一个多相位时钟的数量由下式给出： ñ

10. 发明公开

EP1045518A1 Phase Mixer 审中-公开
标题翻译： Phasenmischer
公开(公告)号：EP1045518A1
公开(公告)日：2000-10-18
申请号：EP00106480.7
申请日：2000-03-25
申请人： Infineon Technologies North America Corp.
发明人： Toosky, Zabih
IPC分类号： H03K5/00 , H03K5/13 , H03L7/099
CPC分类号： H03L7/0996 , H03L7/18
摘要： A phase mixer is provided which locks a signal to a non-integer multiple of a reference signal. A phase mixer according to the present invention is provided which generates non-integer multiples of a stable reference source, such that an output frequency to an input frequency of the phase mixer has a frequency ratio of f out = f in × N N ± M , where N is an integer number of phases of the reference signal and M is an integer less than N and the "+" operation is used when selecting phases in ascending order and the "-" operation is used when selecting phases in descending order. Briefly, the phase mixer according to one embodiment includes a recirculating shift register (108) and a multiplexer (110). The shift register (108) output addresses the multiplexer (110), and the multiplexer (110) in turn selects as the output one of the phases of the reference oscillator. The output of the multiplexer (110) is used to clock the shift register (108). Because the reference oscillator phases are themselves shifted with reference to one another, sequential selection of the phase pulses as output pulses results in an output which is a non-integer multiple of the reference oscillator frequency.
摘要翻译：提供了一种将信号锁定到参考信号的非整数倍的相位混频器。提供了根据本发明的相位混合器，其生成稳定参考源的非整数倍，使得到相位混频器的输入频率的输出频率具有 fout = fin×N DIVIDED N的频率比 +/- M，其中N是参考信号的整数相位，M是小于N的整数，并且在按照升序选择相位时使用“+”运算，“ - ”运算是在按降序选择相位时使用。简而言之，根据一个实施例的相位混合器包括循环移位寄存器（108）和多路复用器（110）。移位寄存器（108）输出寻址复用器（110），并且多路复用器（110）又选择作为参考振荡器的相位的输出一个。复用器（110）的输出用于对移位寄存器（108）进行时钟。由于参考振荡器相位彼此相对移位，所以相位脉冲的顺序选择作为输出脉冲导致作为参考振荡器频率的非整数倍的输出。

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