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1. 发明公开

EP1892838A3 A digital-to-analog converter 审中-公开
标题翻译：数字 - 模拟转换器
公开(公告)号：EP1892838A3
公开(公告)日：2008-04-23
申请号：EP07121037.1
申请日：2003-04-24
申请人： Neuro Solution Corp.
发明人： Koyanagi, Yukio
IPC分类号： H03M1/66 , H03M1/82
CPC分类号： H03M1/668 , H03M1/82
摘要： A digital to analog converter, comprising a digital portion comprising a counter that performs a counting operation responsive to an externally provided clock and reset signal; a comparator that compares a count value of the counter with n-bit digital input; wherein the comparator compares a count value of the counter with a value of the n-bit digital input and outputs one of at least two clock signals responsive to a comparison result; and an analog portion separate from the digital portion, the analog portion comprising a capacitor; plural switches that selectively connect and disconnect the capacitor from one of at least two constant current sources in response to said one of at least two clock signals from the digital portion; and an analog amplifier having an input coupled to the capacitor and an output that provides an analog representation of the n-bit digital input data, wherein the digital portion and the analog portion are connected together only through the reset signal and said at least two clock signals.

2. 发明授权

EP1028530B1 Multi-channel, parallel, matched digital-to-analog conversion method and converter, and analog drive circuit incorporating same 有权
标题翻译：多通道，并行，匹配的数字 - 模拟转换处理和换能器，并因此提供模拟驱动电路
公开(公告)号：EP1028530B1
公开(公告)日：2006-11-15
申请号：EP99118863.2
申请日：1999-09-24
申请人： Agilent Technologies, Inc. (a Delaware corporation)
发明人： Nishimura, Ken A. , Blalock, Travis N.
IPC分类号： H03M1/66 , G09G3/36
CPC分类号： H03M1/662 , H03M1/82

3. 发明公开

EP1262015A1 POWER-CONSERVING EXTERNAL CLOCK FOR USE WITH A CLOCK-DEPENDENT INTEGRATED CIRCUIT 审中-公开
标题翻译：节能时钟使用与中风依赖集成电路
公开(公告)号：EP1262015A1
公开(公告)日：2002-12-04
申请号：EP01906736.2
申请日：2001-01-27
申请人： Semtech New York Corporation
发明人： MARTEN, Victor
IPC分类号： H03B5/36
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： The problem of undesired power consumption in an oscillator during "stop" periods of a device is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line communicating an oscillator "clock" signal. If the device enters a "stop" state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the "no-stop" state. In response to the relatively low current, the apparatus halts oscillation. Later, when the device exits the "stop" state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device. Alternatively the apparatus monitors two oscillator lines by means of an XOR gate, powering down the oscillator when the XOR output goes low and restoring the oscillator when the XOR output goes high.

4. 发明公开

EP0481967A2 Temperature compensation circuit and time delay generatof including the same 失效
标题翻译： Temperaturkompensationsschaltung。
公开(公告)号：EP0481967A2
公开(公告)日：1992-04-22
申请号：EP92200032.8
申请日：1987-11-27
申请人： ANALOG DEVICES, INCORPORATED
发明人： Barrow, Jeffrey George , Brokaw, Adrian Paul
IPC分类号： G05F3/22 , G05F1/567 , G04F1/00 , H03K5/13 , H03M1/06 , H03K4/50
CPC分类号： H03M1/82 , G04F1/005 , G05F1/567 , G05F3/225 , G05F3/227 , H03K4/50 , H03K5/131 , H03K2005/00163 , H03K2005/00182 , H03M1/089 , H03M1/785
摘要： A temperature compensation circuit is disclosed which has a monolithic integrated circuit with at least one integrated resistor (R84) having a first temperature coefficient, and an integrated bias circuit containing a pair of cross-coupled transistors (Q178, Q179). The temperature compensation circuit generates a compensating current (I S ) through a resistor (R S ) external to the integrated circuit, and having a second temperature coefficient different from the first temperature coefficient. The temperature compensation circuit includes a circuit (R76, 408) for passing a temperature-varying current (I t ) through the integrated resistor (R84) to generate a first temperature-varying voltage (V A ). The bias circuit (Q178, Q179) is connected to the integrated resistor (R84) and the external resistor (R S ) so that a second temperature-varying voltage (V B ) is impressed across the external resistor (R S ), which second temperature-varying voltage (V B ) is proportional to the first temperature-varying voltage (V A ) and generates the compensating current (I S ) through the external resistor (R S ).
摘要翻译：公开了一种温度补偿电路，其具有具有至少一个具有第一温度系数的集成电阻器（R84）和包含一对交叉耦合晶体管（Q178，Q179）的集成偏置电路的单片集成电路。温度补偿电路通过集成电路外部的电阻（RS）产生补偿电流（IS），并具有与第一温度系数不同的第二温度系数。温度补偿电路包括用于使温度变化电流（It）通过集成电阻器（R84）的电路（R76,408），以产生第一温度变化电压（VA）。偏置电路（Q178，Q179）连接到集成电阻器（R84）和外部电阻器（RS），使得在外部电阻器（RS）上施加第二温度变化电压（VB），第二温度变化电压（VB）与第一温度变化电压（VA）成比例，并通过外部电阻（RS）产生补偿电流（IS）。

5. 发明公开

EP0344998A1 Digital-to-analogue conversion 失效
标题翻译：数字Analogwandlung。
公开(公告)号：EP0344998A1
公开(公告)日：1989-12-06
申请号：EP89305396.7
申请日：1989-05-26
申请人： BRITISH TELECOMMUNICATIONS public limited company
发明人： Da Franca, Jose de Albuquerque Epifanio , Vital, Joao Paulo Calado Cordeiro , Leme, Carlos Mexia de Almeida de Azeredo
IPC分类号： H03H17/02 , G06J1/00 , H03M1/66
CPC分类号： H03H19/004 , H03M1/82
摘要： The converter incorporates a transversal filter. The filter delays are implemented in digital form prior to conversion into analogue signals (preferably using switched capacitor techniques). One form of switched capacitor converter (with or without filtering) employs a single capacitor, common to a plurality of bits, appropriate weighting of the bits being achieved by controlling the switching.
摘要翻译：该转换器包含横向滤波器。滤波器延迟在转换成模拟信号之前以数字形式实现（优选使用开关电容器技术）。一种形式的开关电容器转换器（具有或不具有滤波）采用通常用于多个位的单个电容器，通过控制切换来实现位的适当加权。

6. 发明公开

EP0156305A3 Digital/analogue converter 失效
标题翻译：数字/模拟转换器
公开(公告)号：EP0156305A3
公开(公告)日：1989-02-08
申请号：EP85103294.6
申请日：1985-03-21
申请人： HITACHI, LTD.
发明人： Noda, Tsutomu , Iso, Yoshimi , Sato, Tetsuo
IPC分类号： H03M1/82
CPC分类号： G11B20/10527 , G11B20/00992 , H03M1/82
摘要： A digital-to-analogue converter for use in a digitally-recorded-signal reproducing apparatus comprises a first constant current source (5, 11, 12; 42, 43, 44), a switch (4; 13, 14; 45, 46, 47) for allowing the constant current of the first constant current source to flow therethrough for a period corresponding to the digital data, a second constant current source (26; 36; 55; 60) generating a current flowing in the direction opposite to that of the current generated by the first constant current source, a switch (27; 37; 56; 61) for allowing the current of the second constant current source to flow therethrough for a predetermined constant period, and an integrator (7,8,9), wherein the sum of the first and second constant currents is integrated by the integrator. The analogue signal outputted by the integrater has a center level in the vicinity of the ground potential level.

7. 发明公开

EP0104578A2 Digital-Analog-Wandler mit Potentialtrennung 失效
标题翻译：数字 - 模拟转换器与隔离。
公开(公告)号：EP0104578A2
公开(公告)日：1984-04-04
申请号：EP83109270.5
申请日：1983-09-19
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Ophoff, Paul Arthur, Ing. grad.
IPC分类号： H03M1/66
CPC分类号： H03M1/82
摘要： Bei dem erfindungsgemäßen Digital-Analog-Wandler folgt auf einen an den digitalen Datenkanal (D) angeschlossenen Zwischenspeicher (1) mit parallelen Speicherplätzen für N bit ein Volladdierer (2), an dessen Eingang auch der Ausgang eines frei laufenden Zählers (4) mit N bit angeschlossen ist. Der Übertragsausgang (Ü) des Volladdierers (2) ist über einen Optokoppler (5) als Potentialtrenner an einen Mittelwertbildner (7) angeschlossen, der aus der am Übertragsausgang (Ü) des Volladdierers auftretenden Impulsfolge, deren Impuls/Pausen-Verhältnis dem im Zwischenspeicher befindlichen Digitalwert entspricht, einen Mittelwert bildet, der am Ausgang als analoges Signal (A) abnehmbar ist. Auch bei mehrkanaliger Ausführung wird nur ein Optokoppler zur Datenübertragung benötigt, von dessen Schalteigenschaften Linearität und Stabilität im wesentlichen abhängen.
Der Umsetzer wird angewandt bei Analysengeräten.
摘要翻译：利用本发明的数字 - 模拟转换器之后的在连接到具有用于N个并行的存储单元（1）的中间罐中的数字数据信道（D）的位全加器（2），在输入端和一个自由运行的计数器（4）用N的输出位连接。全加器的进位输出（B）（2）通过一个光耦合器（5）连接作为分压器到平均单元（7），从所述全加器的进位输出（B），位于所述缓冲存储器的脉冲/间歇比发生的脉冲序列数字值对应，形成一个平均值，其是在输出作为模拟（A）信号可移除的。即使使用多通道执行仅光耦合器需要进行数据传输，根据线性度和稳定性基本上的开关特性。该转换器在分析仪器中使用。

8. 发明公开

EP0100103A1 A pulse width modulation circuit and an analog product forming integration circuit using such modulation circuit 失效
标题翻译：脉冲宽度调制器和积分电路，用于与这样的脉冲宽度调制器形成的模拟产品。
公开(公告)号：EP0100103A1
公开(公告)日：1984-02-08
申请号：EP83107412.5
申请日：1983-07-27
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER ENGINEERING LTD.
发明人： Takagi, Katsuaki , Kita, Yuzo , Hagiwara, Yoshimune , Ogawa, Kazuyoshi , Hara, Hideo
IPC分类号： H03K7/08
CPC分类号： H03M1/82 , H03K7/08
摘要： A pulse width modulation circuit is capable of cancelling the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits (FF3, L1, L2) to an existing pulse width modulation circuit (10, CP3). Such pulse width modulation circuit is used preferably in an integration circuit forming the product of two analog signals.
The offset of the triangular wave signal (VA) is cancelled by inverting either the triangular wave signal with respect to the input signal or the input signal with respect to the triangular wave signal, in every predetermined period. To this end, the circuit eliminates the offset of a comparator (CP3) by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

9. 发明公开

EP3041144A1 INJECTION LOCKED RING OSCILLATOR BASED DIGITAL-TO-TIME CONVERTER AND METHOD FOR PROVIDING A FILTERED INTERPOLATED PHASE SIGNAL 审中-公开
标题翻译：对提供滤波INTER抛光砖相位信号INJEKTIONSVERRIEGELTEM基于环形振荡器的数字 - 时间转换器和方法
公开(公告)号：EP3041144A1
公开(公告)日：2016-07-06
申请号：EP15194395.8
申请日：2015-11-12
申请人： Intel IP Corporation
发明人： PONTON, Davide , PASSAMANI, Antonio , BEVILACQUA, Andrea
IPC分类号： H03M1/82 , H03K5/13 , H03C3/00
CPC分类号： H03M1/662 , G04F10/005 , H03C3/00 , H03K3/0315 , H03K5/131 , H03L7/0998 , H03M1/82 , H04L27/2331
摘要： Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.
摘要翻译：提供装置和数字至时间转换器（DTC）的方法。在一个示例中，DTC可以包括相位内插器和一个环形振荡器。相位内插器可以配置为接收两个或更多个不同的相位信号的数字表示，并进行内插的两个或多个不同相位信号的数字表示在插输出相位信号，以提供。环形振荡器可以被配置成接收内插相位信号，以锁定到一个频率和内插的输出的相位信号的相位，并提供经滤波的相位信号。

10. 发明公开

EP1295397A1 INTENTIONALLY NON-MONOTONIC DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：特别是不单调的数字/模拟转换器
公开(公告)号：EP1295397A1
公开(公告)日：2003-03-26
申请号：EP01906667.9
申请日：2001-01-24
申请人： Semtech New York Corporation
发明人： MARTEN, Victor
IPC分类号： H03M1/12
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： The problem of undesired power consumption in an oscillator during "stop" periods of a device is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line communicating an oscillator "clock" signal. If the device enters a "stop" state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the "no-stop" state. In response to the relatively low current, the apparatus halts oscillation. Later, when the device exits the "stop" state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device. Alternatively the apparatus monitors two oscillator lines by means of an XOR gate, powering down the oscillator when the XOR output goes low and restoring the oscillator when the XOR output goes high.

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