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1. 发明公开

EP3261251A1 A LEVEL SHIFTER AND A METHOD FOR SHIFTING VOLTAGE LEVEL 审中-公开
标题翻译：一种电平转换器和一种转换电压电平的方法
公开(公告)号：EP3261251A1
公开(公告)日：2017-12-27
申请号：EP17177329.4
申请日：2017-06-22
申请人： Minima Processor Oy
发明人： Paasio, Ari , Koskinen, Lauri , Turnquist, Matthew
IPC分类号： H03K3/356 , H03K19/00 , H03K19/096
CPC分类号： H03K19/0185 , H03K3/356113 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/018521 , H03K19/018585 , H03K19/0963
摘要： A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.
摘要翻译：电平移位器包括：第一控制开关（207），用于将输出端连接到第一电源电压（VDDH）以将输出信号设置为高;以及第二控制开关（208），用于将输出端连接到信号地（GND）将输出信号设置为低电平。电平移位器包括用于将输出端子连接到第一电源电压的预充电开关（210），以及用于控制输入信号控制第二控制开关的能力的输入门电路（211）。电平移位器包括用于基于输出信号控制第一控制开关的保持器电路（212）。当输出信号为低时，第一控制开关由第一电源电压控制，并且在输出信号为高时以第二电源电压在第一电源电压与信号地之间控制。

2. 发明公开

EP3255792A1 LOW-RIPPLE LATCH CIRCUIT FOR REDUCING SHORT-CIRCUIT CURRENT EFFECT 有权转让
标题翻译：低纹波锁存电路，用于降低短路电流影响
公开(公告)号：EP3255792A1
公开(公告)日：2017-12-13
申请号：EP17178685.8
申请日：2016-03-10
申请人： MediaTek Inc.
发明人： HO, Chen-Yen , LIN, Yu-Hsin , TSAI, Hung-Chieh , WANG, Tze-Chien
IPC分类号： H03K3/356 , H03M1/08 , H03M1/06 , H03M1/66 , H03M3/00
CPC分类号： H03K3/356113 , H03K3/356121 , H03K3/356191 , H03M1/066 , H03M1/0872 , H03M1/66 , H03M3/464
摘要： A latch circuit (300) includes an input stage (310), an amplifying stage (MN1, MN2, MP1, MP2) and a clock gating circuit (320). The input stage (310) is arranged for receiving at least a clock signal and a data control signal. The amplifying stage (MN1, MN2, MP1, MP2) is coupled to the input stage (310) and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit (320) is coupled to the amplifying stage (MN1, MN2, MP1, MP2), and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.
摘要翻译：锁存电路（300）包括输入级（310），放大级（MN1，MN2，MP1，MP2）和时钟门控电路（320）。输入级（310）被设置用于至少接收时钟信号和数据控制信号。放大级（MN1，MN2，MP1，MP2）耦合到输入级（310）并由供电电压和地电压供电，并且被布置为保持数据值并根据时钟信号输出数据值和数据控制信号。时钟门控电路（320）耦合到放大级（MN1，MN2，MP1，MP2），并且被布置用于避免电源电压和接地电压之间的短路电流。

3. 发明公开

EP2804179A1 Radiation hardened circuit 审中-公开
标题翻译： StrahlungsgehärteteSchaltung
公开(公告)号：EP2804179A1
公开(公告)日：2014-11-19
申请号：EP13305644.0
申请日：2013-05-17
申请人： STMicroelectronics (Crolles 2) SAS , STMicroelectronics Pvt. Ltd , Centre National de la Recherche Scientifique , Université d'Aix-Marseille
发明人： Gasiot, Gilles , Clerc, Sylvain , Yousuf, Junaid , Glorieux, Maximilien
IPC分类号： G11C5/00 , H03K3/037 , H03K3/356 , H03L7/089
CPC分类号： H03K19/0033 , G11C5/005 , H03K3/0375 , H03K3/356121 , H03L7/08 , H03L7/0891 , H03L7/0896 , H03L7/095 , H03L7/18
摘要： The invention concerns a circuit comprising: a data storage element (102); first and second input circuitry (104, 104') coupled respectively to first and second inputs (IN1, IN2) of the data storage element and each comprising a plurality of components adapted to generate, as a function of an initial signal (IN), first and second input signals respectively provided to said first and second inputs; wherein the data storage element comprises a first storage node and is configured such that a voltage state stored at said first storage node is protected from a change in only one of said first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on said first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on said second input signal.
摘要翻译：本发明涉及一种电路，包括：数据存储元件（102）; 第一和第二输入电路（104,104'）分别耦合到数据存储元件的第一和第二输入（IN1，IN2），并且每个包括适于产生作为初始信号（IN）的函数的多个分量，分别提供给所述第一和第二输入的第一和第二输入信号; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化耦合到第一存储节点并且基于所述第一输入信号和由耦合到第一存储节点的第二晶体管的导通状态进行控制，并且基于所述第二输入信号进行控制。

4. 发明公开

EP2502272A4 NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：不挥发锁定电路和逻辑电路半导体器件
公开(公告)号：EP2502272A4
公开(公告)日：2014-03-19
申请号：EP10831470
申请日：2010-10-29
申请人： SEMICONDUCTOR ENERGY LAB
发明人： KATO KIYOSHI , KOYOMA JUN
IPC分类号： H01L27/105 , G11C7/04 , G11C14/00 , G11C16/04 , H01L21/02 , H01L21/28 , H01L21/8234 , H01L21/8242 , H01L27/00 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/66 , H01L29/786 , H03K3/037 , H03K3/286 , H03K3/356 , H03K19/00 , H03K19/0948 , H03K19/096
CPC分类号： H03K3/356104 , G11C7/04 , G11C14/0063 , G11C16/045 , G11C2211/4016 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/28202 , H01L21/28211 , H01L27/105 , H01L27/1203 , H01L27/1225 , H01L29/6659 , H03K3/0375 , H03K3/286 , H03K3/356 , H03K3/356121 , H03K3/356173

5. 发明公开

EP2342823A2 LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME 审中-公开
标题翻译：锁定结构，分频器和方法进行操作
公开(公告)号：EP2342823A2
公开(公告)日：2011-07-13
申请号：EP09792735.4
申请日：2009-09-18
申请人： QUALCOMM Incorporated
发明人： ZHANG, Kun , BARNETT, Kenneth
IPC分类号： H03K3/356
CPC分类号： H03K3/356121 , H03K5/1565 , H03K23/544
摘要： A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

6. 发明公开

EP2207262A3 Clocked d-type flip flop circuit 审中-公开
标题翻译：主频D触发器电路
公开(公告)号：EP2207262A3
公开(公告)日：2011-06-29
申请号：EP09175591.8
申请日：2009-11-10
申请人： AU Optronics Corporation
发明人： Chen, Chung-Chun , Yang, Kun-Yen , Liao, Wei-Chien
IPC分类号： H03K3/356
CPC分类号： H03K3/356121 , H03K3/356156
摘要： A clocked D-type Flip-Flop circuit has a transmission gate to admit an input data and to provide an intermediate output to a clock-controlled inverter based on the clock signals. The clock-controlled inverter is used as a latch for latching the output signal from the transmission gate and releases the latched signal by the same clock signals to an output inverter. The output of the output inverter is the Q terminal of the Flip-Flop circuit. Another output inverter is used to invert the signal from the Q terminal into a complementary output signal. In one of the embodiments of the present invention, another transmission gate is used to condition the complementary output signal.

7. 发明授权

EP1246361B1 Input circuit 有权
标题翻译：输入电路
公开(公告)号：EP1246361B1
公开(公告)日：2010-09-08
申请号：EP02006598.3
申请日：2002-03-22
申请人： NEC Electronics Corporation
发明人： Watarai, Seiichi
IPC分类号： H03K3/356
CPC分类号： H03K3/356139 , H03K3/012 , H03K3/356121

8. 发明公开

EP1394944A1 Differential CMOS latch and digital quadrature LO generator using same 有权
标题翻译：差分CMOS-Kippschaltung在einem Lokalquadratroroszillator
公开(公告)号：EP1394944A1
公开(公告)日：2004-03-03
申请号：EP03102654.5
申请日：2003-08-26
申请人： Texas Instruments Incorporated
发明人： Fang, Sher J. , Lee, See T. , Bellaouar, Abdellatif
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： A wideband digital quadrature local oscillator (LO) generator (300) using clocked-CMOS (C 2 MOS) latches (302, 304) can operate at very high frequencies, while consuming less current and having lower phase noise as compared to prior art quadrature LO generators using Source-coupled logic (SCL) latches. In addition, the LO generator (300) has no low frequency limit and can output rail-to-rail square waves.
摘要翻译：使用时钟CMOS（C 2 MOS）锁存器（302,304）的宽带数字正交本地振荡器（LO）发生器（300）可以在非常高的频率下工作，同时消耗更少的电流并且具有比以前更低的相位噪声使用源极耦合逻辑（SCL）锁存器的正交LO发生器。此外，LO发生器（300）没有低频限制，并且可以输出轨至轨方波。

9. 发明授权

EP0585925B1 Voltage converting circuit 失效
标题翻译：电压转换器电路
公开(公告)号：EP0585925B1
公开(公告)日：1998-07-08
申请号：EP93114081.8
申请日：1993-09-02
申请人： NEC CORPORATION
发明人： Tamagawa, Akio, c/o NEC Corporation
IPC分类号： H02M3/07
CPC分类号： H03K3/356026 , H02M3/07 , H02M2001/009 , H03K3/356121

10. 发明公开

EP0500588A4 HIGH SPEED COMPARATOR WITH OFFSET CANCELLATION 失效
标题翻译：具有偏移消除的高速比较器
公开(公告)号：EP0500588A4
公开(公告)日：1993-05-12
申请号：EP90915886
申请日：1990-10-16
申请人： VLSI TECHNOLOGY, INC.
发明人： LIU, EDWARD WAI YEUNG
IPC分类号： H03K5/08 , H03K3/356
CPC分类号： H03K3/356121 , H03K3/356026

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