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1. 发明公开

EP3350928A1 HIGH-SPEED PROGRAMMABLE CLOCK DIVIDER 有权
公开(公告)号：EP3350928A1
公开(公告)日：2018-07-25
申请号：EP16754368.5
申请日：2016-08-10
申请人： Qualcomm Incorporated
发明人： AGRAWAL, Neha , MOHAMAD, Sajin , LEE, Chulkyu
IPC分类号： H03K21/10 , H03K23/64
CPC分类号： H03K7/06 , G06F1/08 , H03K3/037 , H03K19/21 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/64
摘要： Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

2. 发明公开

EP1605594A3 Clock frequency divider and trigger signal generation circuit for same 有权
标题翻译：时钟分频器和相应的电路，用于触发信号生成
公开(公告)号：EP1605594A3
公开(公告)日：2008-12-10
申请号：EP05251053.4
申请日：2005-02-23
申请人： FUJITSU LIMITED
发明人： Marutani, Masazumi, c/o Fujitsu Limited
IPC分类号： H03K23/44 , H03K23/64
CPC分类号： H03K23/64 , H03K23/44
摘要： A clock frequency divider is provided which has first to Pth (where P is an integer) sub-counters (SC1 to SCP), each capable of counting M+1 clock pulses and provided in parallel, and first to Pth clock signals (IC1 to ICP) are provided to the sub-counters, which have the same period as a reference clock signal (RCLK) and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first to Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.

3. 发明公开

EP3419177A1 VARIABLE FREQUENCY DIVIDER 有权
公开(公告)号：EP3419177A1
公开(公告)日：2018-12-26
申请号：EP16894379.3
申请日：2016-03-16
申请人： Mitsubishi Electric Corporation
发明人： YANAGIHARA, Yuki , TSUTSUMI, Koji
IPC分类号： H03K23/64 , H03L7/18
CPC分类号： H03K23/64 , H03K23/667 , H03L7/18 , H03L7/193
摘要： A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

4. 发明授权

EP1605594B1 Clock frequency divider and trigger signal generation circuit for same 有权
标题翻译：时钟分频器和相应的电路，用于触发信号生成
公开(公告)号：EP1605594B1
公开(公告)日：2010-04-07
申请号：EP05251053.4
申请日：2005-02-23
申请人： FUJITSU LIMITED
发明人： Marutani, Masazumi, c/o Fujitsu Limited
IPC分类号： H03K23/44 , H03K23/64
CPC分类号： H03K23/64 , H03K23/44

5. 发明公开

EP1605594A2 Clock frequency divider and trigger signal generation circuit for same 有权
标题翻译： Taktteiler und entsprechende Schaltung zur Triggersignalerzeugung
公开(公告)号：EP1605594A2
公开(公告)日：2005-12-14
申请号：EP05251053.4
申请日：2005-02-23
申请人： FUJITSU LIMITED
发明人： Marutani, Masazumi, c/o Fujitsu Limited
IPC分类号： H03K23/44
CPC分类号： H03K23/64 , H03K23/44
摘要： A clock frequency divider is provided which has first to Pth (where P is an integer) sub-counters (SC1 to SCP), each capable of counting M+1 clock pulses and provided in parallel, and first to Pth clock signals (IC1 to ICP) are provided to the sub-counters, which have the same period as a reference clock signal (RCLK) and are sequentially shifted by 1/P of the period of the reference clock signal. Of the first to Pth sub-counters, when the Nth sub-counter (where N is an arbitrary number from 1 to P) finishes counting a prescribed number M of reference clock pulses, all the other sub-counters are initialized, or, at least the (N+1)th sub-counter is initialized.
摘要翻译：提供了一个时钟分频器，其具有第一至第P（其中P是整数）子计数器（SC1至SCP），每个子计数器可以对M + 1个时钟脉冲进行并行并行并行提供，第一至第P个时钟信号（IC1至 ICP）被提供给子计数器，它们与参考时钟信号（RCLK）具有相同的周期，并且被顺序地移动参考时钟信号的周期的1 / P。在第一到第P子计数器中，当第N个子计数器（其中N是从1到P的任意数字）完成对规定数量M的参考时钟脉冲的计数时，所有其他子计数器被初始化，或者在至少第（N + 1）个子计数器被初始化。

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