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1. 发明授权

EP0136204B1 Control of signal timing apparatus in automatic test systems using minimal memory 失效
标题翻译：使用最小存储器对自动测试系统中的信号时序设备进行控制
公开(公告)号：EP0136204B1
公开(公告)日：1988-04-06
申请号：EP84401606.3
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Herlein, Richard F.
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

2. 发明公开

EP0226614A1 PULSE ALIGNMENT SYSTEM 失效
标题翻译：系统实现了脉冲CV平等。
公开(公告)号：EP0226614A1
公开(公告)日：1987-07-01
申请号：EP86903884.0
申请日：1986-05-23
申请人： Hughes Aircraft Company
发明人： BEYERBACH, Daniel, M. , SCOTT, William, L. , GOCZALK, Robert, W.
IPC分类号： H03F3 , H03K5
CPC分类号： H03K5/131 , H03F3/58 , H03K5/135 , H03K2005/00254
摘要： Un système d'alignement automatique de deux impulsions convient particulièrement pour aligner l'impulsion de courant cathodique appliquée à un amplificateur (1) à tube à ondes progressives (TWT) avec l'impulsion HF d'excitation de façon à augmenter l'efficacité de l'amplificateur TWT (1). Le système comprend un circuit de retard programmable (40, 45) pour retarder sélectivement l'impulsion de courant cathodique après le déclenchement du système. Un signal d'alignement des impulsions indique quand les deux impulsions sont alignées. Une unité de commande (60) du système applique un algorithme d'étalonnage afin de modifier itérativement le retard tout en contrôlant le signal d'alignement pour déterminer l'étalonnage du retard qui provoque l'alignement des impulsions. L'étalonnage du retard est enregistré dans une mémoire et utilisé par l'unité de commande (60) pendant le mode normal de fonctionnement pour ajuster le circuit de retard programmable selon la valeur étalonné.

3. 发明公开

EP0304450A1 METHOD AND APPARATUS FOR OBTAINING HIGH FREQUENCY RESOLUTION OF A LOW FREQUENCY SIGNAL 失效
标题翻译：方法和装置率较高分辨率的信号低频。
公开(公告)号：EP0304450A1
公开(公告)日：1989-03-01
申请号：EP88901993.0
申请日：1988-01-28
申请人： HUGHES AIRCRAFT COMPANY
发明人： UNDERWOOD, George, D.
IPC分类号： H03K3 , H03K5
CPC分类号： H03K3/017 , H03K5/05 , H03K5/131 , H03K2005/00234 , H03K2005/00254
摘要： Procédé et appareil permettant d'obtenir une résolution de haute fréquence d'un signal de données de basse fréquence. L'invention comprend une logique de sélection de basse fréquence (27) pour produire le signal de données ayant une résolution de basse fréquence, une logique d'automate fini de basse fréquence (29) pour déterminer si le signal de données est résolu d'après des caractéristiques prédéterminées de résolution de haute fréquence, un circuit produisant un signal de correction pour modifier le signal de données en fonction de la résolution de haute fréquence, et une logique de haute fréquence (17) pour modifier le signal de données en réponse au signal de correction de basse fréquence. La logique de haute fréquence (17) modifie sélectivement le chemin des données de basse fréquence en réponse au signal de correction pour modifier le signal de données de basse fréquence et obtenir une résolution de haute fréquence.

4. 发明授权

EP0136206B1 Method and apparatus for monitoring automated testing of electronic circuits 失效
标题翻译：用于监测电子电路自动测试的方法和装置
公开(公告)号：EP0136206B1
公开(公告)日：1988-03-30
申请号：EP84401609.7
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Schinabeck, John
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

5. 发明公开

EP0196167A3 Method for adjusting a time delay 失效
标题翻译：调整时间延迟的方法
公开(公告)号：EP0196167A3
公开(公告)日：1987-10-21
申请号：EP86301474
申请日：1986-02-28
申请人： TEKTRONIX, INC.
发明人： Sutton, Steven R. , Hoeren, Gerd H.
IPC分类号： G01R31/28 , G06F11/26 , H03K05/13
CPC分类号： G01R31/318307 , G01R31/31912 , H03K5/131 , H03K2005/00254
摘要： A method for adjusting a time delay of a signal with respect to a reference event comprises the steps of displaying a graphical representation of the delay time on a display terminal, modifying the displayed graphical depiction to indicate a different time delay, and then adjusting the time delay of the signal to match the modified time delay indicated by the displayed graphical depiction. The display terminal is controlled by a display controller and the graphical depiction of the delay time is modified by an operator using a first means to transmit a first indicating signal to the display controller and a second means to transmit a second indicating signal to the display controller. Each time the controller detects a first indicating signal, the graphically displayed delay time is incremented and each time the controller detects a second indicating signal, the graphically displayed delay time is decremented. The controller automatically adjusts the actual test signal delay time after the displayed delay time has been adjusted.

6. 发明公开

EP0136205A1 Method and apparatus for applying and monitoring programmed test signals during automated testing of electronic circuits 失效
标题翻译：为应用和监督的方法和设备的电子电路的自动测试过程中编程的测试信号。
公开(公告)号：EP0136205A1
公开(公告)日：1985-04-03
申请号：EP84401608.9
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Schinabeck, John , Murdock, James R.
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Progammable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing. Other features are also disclosed.
摘要翻译：的测试信号施加和监测电路耦合到电子装置的销的多个被测试以迫使测试激励下测试信号到该装置的输入引脚。当所述设备被测试的响应信号受到监控。施加和监测电路中的每个测试信号包括节点被耦合到所述被测装置的销，一个数字编程源用于通过第一开关供给的测试信号连接到所述节点，和一个比较电路由连接到节点用于相对于编程的参考电平指示响应信号的相对幅度第二开关。的数字编程的源包括用于功能测试期间提供门控电压 - 电流交叉强制功能当被测试的设备被连接，以最小化干扰，并保护超出公差装置。 Progammable电压和电流值确定合适的窗口，以确保一个nonambiguous合格/去测试期间产生的。其他功能使游离缺失盘。

7. 发明授权

EP0394166B1 Method for operating a programmable delay circuit and programmable delay circuit 失效
标题翻译：一种操作可编程延迟电路和可编程延迟电路的方法。
公开(公告)号：EP0394166B1
公开(公告)日：1994-12-07
申请号：EP90480040.6
申请日：1990-03-13
申请人： International Business Machines Corporation
发明人： Fisher, Jeffrey Herbert , Grasso, Lawrence Joseph , Hoffman, Dale Eugene , Skooglund, Daniel Edward , Young, Diane Kay
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00097 , H03K2005/00104 , H03K2005/00247 , H03K2005/00254

8. 发明授权

EP0304450B1 METHOD AND APPARATUS FOR OBTAINING HIGH FREQUENCY RESOLUTION OF A LOW FREQUENCY SIGNAL 失效
标题翻译：获取低频信号高频分辨率的方法和装置
公开(公告)号：EP0304450B1
公开(公告)日：1992-04-01
申请号：EP88901993.1
申请日：1988-01-28
申请人： Hughes Aircraft Company
发明人： UNDERWOOD, George, D.
IPC分类号： H03K5/05 , H03K5/13
CPC分类号： H03K3/017 , H03K5/05 , H03K5/131 , H03K2005/00234 , H03K2005/00254
摘要： A method and apparatus for obtaining high frequency resolution of a low frequency data signal are provided. The invention comprises a low frequency select logic (27) for generating the data signal having low frequency resolution, low frequency state machine logic (29) for determining whether the data signal is resolved to predetermined high frequency resolution characteristics and circuitry for generating a correction signal to modify the data signal to high frequency resolution, and high frequency logic (17) for modifying the data signal in response to the low frequency correction signal. The high frequency logic (17) operates to selectively modify the path of low frequency data in response to the correction signal to modify the low frequency data signal to obtain high frequency resolution .

9. 发明公开

EP0394166A3 Method for operating a programmable delay circuit and programmable delay circuit 失效
标题翻译：运行可编程延迟电路和可编程延迟电路的方法
公开(公告)号：EP0394166A3
公开(公告)日：1991-03-27
申请号：EP90480040.6
申请日：1990-03-13
申请人： International Business Machines Corporation
发明人： Fisher, Jeffrey Herbert , Grasso, Lawrence Joseph , Hoffman, Dale Eugene , Skooglund, Daniel Edward , Young, Diane Kay
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00097 , H03K2005/00104 , H03K2005/00247 , H03K2005/00254
摘要： A method of operating a delay circuit to impose a selected delay on an electronic signal, the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.

10. 发明公开

EP0322308A2 Delay line control system for automatic test equipment 失效
标题翻译： VerzögerungsliniensteuerungssystemfürautomatischesTestgerät。
公开(公告)号：EP0322308A2
公开(公告)日：1989-06-28
申请号：EP88403258.2
申请日：1988-12-21
申请人： SCHLUMBERGER TECHNOLOGIES, INC.
发明人： Herlein, Richard F. , Davis, Jeffrey A.
IPC分类号： H03K5/13 , G06F11/26
CPC分类号： H03K5/131 , G01R31/3191 , G01R31/31922 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory (44) which stores information representing the higher order bits of a time delay, while vernier memories (70, 72) store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data.
The base delay memory (44) controls at least two counters (40, 42) in independent signal paths, while the vernier (70, 72) and offset memories control appropriate deskew units (60, 62) for further delaying the counter (40, 42) output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.
摘要翻译：公开了一种能够在自动测试系统中以精确期望的时间提供信号的系统。该装置包括存储表示时间延迟的较高位的信息的基本延迟存储器（44），而游标存储器（70,72）存储与时间延迟的较低位相关的信息。偏移存储器可存储校准数据。基本延迟存储器（44）控制独立信号路径中的至少两个计数器（40,42），而游标（70,72）和偏移存储器控制适当的去偏移单元（60,62），用于进一步延迟计数器 42）输出信号。该系统能够共享资源，但不需要重复加载校正数据进行偏移校正操作。

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