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1. 发明授权

EP0136204B1 Control of signal timing apparatus in automatic test systems using minimal memory 有权
标题翻译：使用最小存储器对自动测试系统中的信号时序设备进行控制
公开(公告)号：EP0136204B1
公开(公告)日：1988-04-06
申请号：EP84401606.3
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Herlein, Richard F.
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

2. 发明公开

EP0226614A1 PULSE ALIGNMENT SYSTEM 失效
标题翻译：系统实现了脉冲CV平等。
公开(公告)号：EP0226614A1
公开(公告)日：1987-07-01
申请号：EP86903884.0
申请日：1986-05-23
申请人： Hughes Aircraft Company
发明人： BEYERBACH, Daniel, M. , SCOTT, William, L. , GOCZALK, Robert, W.
IPC分类号： H03F3 , H03K5
CPC分类号： H03K5/131 , H03F3/58 , H03K5/135 , H03K2005/00254
摘要： Un système d'alignement automatique de deux impulsions convient particulièrement pour aligner l'impulsion de courant cathodique appliquée à un amplificateur (1) à tube à ondes progressives (TWT) avec l'impulsion HF d'excitation de façon à augmenter l'efficacité de l'amplificateur TWT (1). Le système comprend un circuit de retard programmable (40, 45) pour retarder sélectivement l'impulsion de courant cathodique après le déclenchement du système. Un signal d'alignement des impulsions indique quand les deux impulsions sont alignées. Une unité de commande (60) du système applique un algorithme d'étalonnage afin de modifier itérativement le retard tout en contrôlant le signal d'alignement pour déterminer l'étalonnage du retard qui provoque l'alignement des impulsions. L'étalonnage du retard est enregistré dans une mémoire et utilisé par l'unité de commande (60) pendant le mode normal de fonctionnement pour ajuster le circuit de retard programmable selon la valeur étalonné.

3. 发明授权

EP0196167B1 Method for adjusting a time delay 失效
标题翻译：调整时间延迟的方法
公开(公告)号：EP0196167B1
公开(公告)日：1991-07-17
申请号：EP86301474.2
申请日：1986-02-28
申请人： TEKTRONIX, INC.
发明人： Sutton, Steven R. , Hoeren, Gerd H.
IPC分类号： G01R31/28 , G06F11/26 , H03K5/13
CPC分类号： G01R31/318307 , G01R31/31912 , H03K5/131 , H03K2005/00254

4. 发明公开

EP0322308A3 Delay line control system for automatic test equipment 失效
标题翻译：用于自动测试设备的延迟线控制系统
公开(公告)号：EP0322308A3
公开(公告)日：1989-11-15
申请号：EP88403258.2
申请日：1988-12-21
申请人： SCHLUMBERGER TECHNOLOGIES, INC.
发明人： Herlein, Richard F. , Davis, Jeffrey A.
IPC分类号： H03K5/13 , G06F11/26
CPC分类号： H03K5/131 , G01R31/3191 , G01R31/31922 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory (44) which stores information representing the higher order bits of a time delay, while vernier memories (70, 72) store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory (44) controls at least two counters (40, 42) in independent signal paths, while the vernier (70, 72) and offset memories control appropriate deskew units (60, 62) for further delaying the counter (40, 42) output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

5. 发明公开

EP0174409A1 Formatter for high speed test system 失效
标题翻译： FormerungsanordnungfürHochgeschwindigkeits-Testsystem。
公开(公告)号：EP0174409A1
公开(公告)日：1986-03-19
申请号：EP84401607.1
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Herlein, Richard F.
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： Circuitry required in an automatic digital integrated circuit tester to control the application of timed data pulses to the inputs to the device under test, the circuitry to generate strobe signals to control comparators connected to the outputs of the device under test, and the circuitry to decode error signals is implemented in a completely flexible, programmable architecture on a single emitter coupled logic gate array integrated circuit. Each such formatter circuit can control two device under test pins.
Every possible critical signal path to the device under test is routed over a separate signal line which allows each signal path having a different propagation delay to be aligned in time by a deskewing system in order to minimize timing errors. Signals that control the driver circuits that apply data to the device under test inputs pins are separated into a SET signal line and a RESET signal line, due to the difference in propagation delay for the driver when driving the device under test input high versus driving it low. Similarly, the strobe signals to the comparators connected to the device under test output pins are separated into a high level strobe and a low level strobe, due to the difference in propagation delay for the comparator when comparing the device under test output to a high level reference versus a low level reference.
The device under test input transitions and output strobes are not fixed in time with respect to the system clock, but are referenced to it which allows the drive data cycles and the compare data cycles to be somewhat independent of the system clock, permitting them to overlap and cross test period boundaries without requiring test vectors to be changed.
The error correlator decodes the error signals produced by incorrect device under test outputs. Using timing signals derived from the clocks used to control the drive data for the device under test inputs, and the clocks used to generate strobes to control the comparators, the error correlator correctly decodes error signals and logs them in the compare memory location corresponding to the proper test vector.
摘要翻译：自动数字集成电路测试仪所要求的电路，用于控制定时数据脉冲对被测设备的输入的应用，产生选通信号的电路，用于控制连接到待测器件输出的比较器，以及解码电路误差信号在单个发射极耦合逻辑门阵列集成电路上以完全灵活的可编程架构实现。每个这样的格式器电路可以控制两个器件在测试引脚下。到被测设备的每个可能的关键信号路径被路由在单独的信号线上，其允许具有不同传播延迟的每个信号路径在时间上由偏移校正系统对准，以便最小化定时误差。控制驱动电路的信号，将数据应用到被测器件输入引脚，由于驱动器件的驱动器输入高电平而对驱动器的传播延迟差异，因此将其分离为SET信号线和RESET信号线低。类似地，由于在将被测器件的输出与较高电平进行比较时比较器的传播延迟差异，向连接到待测器件的输出引脚的比较器的选通信号分为高电平选通和低电平选通参考与低级别参考。被测器件输入转换和输出选通在系统时钟上并不是及时固定的，而是参考它，允许驱动数据周期和比较数据周期在某种程度上与系统时钟无关，从而允许它们重叠和交叉测试周期边界，而不需要对测试向量进行充电。误差相关器解码由不正确的测试输出设备产生的误差信号。使用从用于控制待测器件的驱动数据的时钟导出的定时信号，以及用于产生选通脉冲以控制比较器的时钟，误差相关器正确地解码错误信号并将它们记录在对应于正确的测试向量。

6. 发明公开

EP0136207A1 Test period generator for automatic test equipment 有权
标题翻译： Prüfperiodengeneratorfürautomatische Testanordnung。
公开(公告)号：EP0136207A1
公开(公告)日：1985-04-03
申请号：EP84401610.5
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： West, Burnell G. , Herlein, Richard F.
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.
摘要翻译：定时子系统10包括若干测试周期发生器，用于向被测设备提供各种定时信号。主，次要和自由运行周期发生器各自向多路复用器18提供各种定时信号，多路复用器18选择性地将定时信号连接到定时发生器20.中央处理单元28向周期发生器和定时发生器提供数据以定义它们各自的定时信号。由主周期发生器12产生的定时信号定义总体测试速率。次周期发生器14在主时钟信号的周期内产生多个定时信号以允许更高的时钟速率。与主时钟周期无关的定时信号由自由运行周期发生器16产生。外部同步器电路26提供从被测器件22到主周期发生器的反馈回路。参考驱动器触发延迟电路27提供用于校准定时发生器的装置。三个周期发生器中的每一个包括交替地产生重叠定时信号的两个相互连接的定时间隔发生器30和40。每个定时间隔发生器包括停止重启振荡器32，计数器34和延迟线游标36。在接收到起始信号时，振荡器停止并重新启动以将其时钟脉冲对准起始信号。振荡器输出时钟计数器，当达到预先选定的数字时，该计数器向游标器提供信号。游标器延迟计数器信号预先设定的延迟并发出指示周期结束的信号。

7. 发明公开

EP0136206A1 Method and apparatus for monitoring automated testing of electronic circuits 有权
标题翻译：为应用和监督的方法和设备的电子电路的自动测试过程中编程的测试信号。
公开(公告)号：EP0136206A1
公开(公告)日：1985-04-03
申请号：EP84401609.7
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Schinabeck, John
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being testes to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested. Other features are also disclosed.
摘要翻译：信号施加和监控电路的多个耦合到出名迫使测试激励信号表示走上被测器件的输入引脚的逻辑状态或其他参数的电子设备的引脚。当设备被测试的刺激信号的响应进行监视。施加和监测电路中的每个信号包括节点被耦合到所述被测装置的销，连接至节点，用于提供测试偏置信号，连接到节点的比较电路，用于指示的相对大小的设备供电测试偏置信号相对于节点处的偏置电平，并且响应于通过该比较电路产生的输出信号的锁存电路。装置电源被包括用于提供测试偏置信号的功能测试期间测试功耗。电源装置的转换进行监测和锁存用于提供所述设备的功率消耗的一个记录被测试。其他功能使游离缺失盘。

8. 发明公开

EP0136204A2 Control of signal timing apparatus in automatic test systems using minimal memory 有权
标题翻译： Kontrolle eines Signaltaktgebers in automatischen Testsystemen unter Verwendung eines Minimalspeichers。
公开(公告)号：EP0136204A2
公开(公告)日：1985-04-03
申请号：EP84401606.3
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Herlein, Richard F.
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.
摘要翻译：公开了一种能够在自动测试系统中以精确期望的时间提供信号的系统。该装置包括存储与基本时间延迟有关的信息的基本延迟存储器，而游标存储器存储与基本时间延迟相关的定时校正的信息。基本延迟存储器控制计数器，而校正存储器控制游标去偏移装置，用于进一步延迟来自计数器的输出信号。为了防止游标存储器的进位影响基本延迟存储器，游标存储器的最高有效位与基本延迟存储器的最低有效位具有相同的意义。游标存储器的最高有效位也被连接以驱动计数器，实际上为计数器提供两个最低有效位，并且使得单个基本延迟存储器能够控制多于一个信号定时路径。

9. 发明公开

EP0304450A1 METHOD AND APPARATUS FOR OBTAINING HIGH FREQUENCY RESOLUTION OF A LOW FREQUENCY SIGNAL 失效
标题翻译：方法和装置率较高分辨率的信号低频。
公开(公告)号：EP0304450A1
公开(公告)日：1989-03-01
申请号：EP88901993.0
申请日：1988-01-28
申请人： HUGHES AIRCRAFT COMPANY
发明人： UNDERWOOD, George, D.
IPC分类号： H03K3 , H03K5
CPC分类号： H03K3/017 , H03K5/05 , H03K5/131 , H03K2005/00234 , H03K2005/00254
摘要： Procédé et appareil permettant d'obtenir une résolution de haute fréquence d'un signal de données de basse fréquence. L'invention comprend une logique de sélection de basse fréquence (27) pour produire le signal de données ayant une résolution de basse fréquence, une logique d'automate fini de basse fréquence (29) pour déterminer si le signal de données est résolu d'après des caractéristiques prédéterminées de résolution de haute fréquence, un circuit produisant un signal de correction pour modifier le signal de données en fonction de la résolution de haute fréquence, et une logique de haute fréquence (17) pour modifier le signal de données en réponse au signal de correction de basse fréquence. La logique de haute fréquence (17) modifie sélectivement le chemin des données de basse fréquence en réponse au signal de correction pour modifier le signal de données de basse fréquence et obtenir une résolution de haute fréquence.

10. 发明授权

EP0136206B1 Method and apparatus for monitoring automated testing of electronic circuits 有权
标题翻译：用于监测电子电路自动测试的方法和装置
公开(公告)号：EP0136206B1
公开(公告)日：1988-03-30
申请号：EP84401609.7
申请日：1984-08-01
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Schinabeck, John
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

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