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1. 发明公开

EP1829106A2 BODY-BIASED PMOS PROTECTION AGAINST ELECTROTATIC DISCHARGE 审中-公开
标题翻译：体偏置PMOS保护静电放电
公开(公告)号：EP1829106A2
公开(公告)日：2007-09-05
申请号：EP05852423.2
申请日：2005-11-30
申请人： Texas Instruments Incorporated
发明人： SALLING, Craig, T. , DUVVURY, Charvaka , BOSELLI, Gianluca
IPC分类号： H01L23/62
CPC分类号： H01L27/0277
摘要： A protection circuit for protecting an integrated circuit pad (201) against an ESD pulse comprises a discharge circuit having an elongated MOS transistor (202) (preferably pMOS) in a substrate (205) (preferably n-type). The discharge circuit is operable to discharge the ESD pulse to the pad, to ground (203). The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component (221) determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor (222) (for example about 40 to 60 Ω) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion. A plurality of contacts to the substrate connects to the resistor so that the voltage drop is uniformly impressed on the substrate to ensure uniform turn-on of the elongated transistor for uniform pulse discharge.

2. 发明公开

EP1946381A2 LOW CAPACITANCE SCR WITH TRIGGER ELEMENT 审中-公开
标题翻译：较差的可控硅触发要素能力
公开(公告)号：EP1946381A2
公开(公告)日：2008-07-23
申请号：EP06816769.1
申请日：2006-10-11
申请人： Texas Instruments Incorporated
发明人： BOSELLI, Gianluca
IPC分类号： H01L29/74
CPC分类号： H01L29/87 , H01L27/0262 , H01L27/0817 , H01L29/66121 , H03K17/0403 , H03K17/08108
摘要： A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element (522). A first well region (504) of a first conductivity type formed within a semiconductor body (502). A first region (510) of the first conductivity type is formed within the first well region. A second region (512) of a second conductivity type is formed with the first well region. A second well region (506) having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region (514) of the first conductivity type is formed within the second well region. A fourth region (516) of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad (518) is connected to the second region. A second terminal (520) is connected to the third region, the fourth region, and the trigger element. In operation, the first terminal conducts current to the second terminal during a low impedance state in response to the altered trigger voltage being applied to the first terminal.

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