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1. 发明公开

EP2717300A4 SEMICONDUCTOR DEVICE 有权
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP2717300A4
公开(公告)日：2015-04-22
申请号：EP12790013
申请日：2012-05-16
申请人： SONY CORP
发明人： FUJII NOBUTOSHI , KAGAWA YOSHIHISA
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/58 , H01L25/00 , H01L27/00 , H01L27/14
CPC分类号： H01L23/498 , H01L23/49866 , H01L23/522 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L27/14636 , H01L27/1464 , H01L2224/05547 , H01L2224/05571 , H01L2224/0603 , H01L2224/06131 , H01L2224/06133 , H01L2224/0616 , H01L2224/06517 , H01L2224/08123 , H01L2224/08147 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/01029 , H01L2924/12043 , H01L2924/13091 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction.
摘要翻译：第一半导体器件包括：第一布线层，包括第一层间绝缘膜，第一电极焊盘和第一虚设电极，第一电极焊盘嵌入第一层间绝缘膜中，并且一个表面位于与一个相同的平面上所述第一层间绝缘膜的表面和所述第一虚设电极嵌入在所述第一层间绝缘膜中，所述第一层间绝缘膜的一个表面位于与所述第一层间绝缘膜的所述一个表面相同的平面上，并且设置在所述第一电极焊盘的周围; 以及包括第二层间绝缘膜，第二电极焊盘和第二虚设电极的第二布线层，所述第二电极焊盘嵌入在所述第二层间绝缘膜中，所述第二层间绝缘膜的一个表面位于与所述第二中间层的一个表面相同的表面上绝缘膜，并且被接合到第一电极焊盘，并且第二虚设电极具有位于与位于更靠近第二层间绝缘膜的第一层间绝缘膜的表面相同的平面上的第一虚拟电极，设置在第二电极焊盘周围，并且被接合到第一虚拟电极。第二半导体器件包括：第一半导体部分，包括第一电极，所述第一电极形成在位于接合界面更靠近并沿第一方向延伸的表面上; 以及第二半导体部分，包括第二电极，并且设置成在所述接合界面处接合到所述第一半导体部分，所述第二电极接合到所述第一电极并沿与所述第一方向相交的第二方向延伸。

2. 发明公开

EP2448861A1 PROCÉDÉ DE COLLAGE CUIVRE-CUIVRE SIMPLIFIÉ 有权
标题翻译：简化的铜 - 铜接合方法
公开(公告)号：EP2448861A1
公开(公告)日：2012-05-09
申请号：EP10726987.0
申请日：2010-07-01
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives , STMicroelectronics (Crolles 2) SAS
发明人： DI CIOCCIO, Léa , GUEGUEN, Pierric , RIVOIRE, Maurice
IPC分类号： B81C1/00
CPC分类号： B81C1/00269 , B81C1/00301 , B81C2203/0109 , B81C2203/019 , B81C2203/038 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05547 , H01L2224/08148 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2924/1461 , H01L2924/00
摘要： A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.

3. 发明公开

EP3350829A1 COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
公开(公告)号：EP3350829A1
公开(公告)日：2018-07-25
申请号：EP16847008.6
申请日：2016-08-03
申请人： Micron Technology, Inc.
发明人： MARIOTTINI, Giorgio , VADHAVKAR, Sameer , HUANG, Wayne , CHANDOLU, Anilkumar , BOSSLER, Mark
IPC分类号： H01L23/00 , H01L23/31 , H01L23/488 , H01L21/60
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/02135 , H01L2224/0219 , H01L2224/03013 , H01L2224/0346 , H01L2224/03472 , H01L2224/0361 , H01L2224/03906 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05082 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05547 , H01L2224/05553 , H01L2224/05555 , H01L2224/05565 , H01L2224/05568 , H01L2224/05644 , H01L2224/05655 , H01L2224/05684 , H01L2224/05686 , H01L2224/05687 , H01L2224/10145 , H01L2224/114 , H01L2224/11472 , H01L2224/13018 , H01L2224/13023 , H01L2224/13026 , H01L2224/13109 , H01L2224/13111 , H01L2224/94 , H01L2924/014 , H01L2924/07025 , H01L2924/3651 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/01047 , H01L2924/053
摘要： The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

4. 发明公开

EP2445000A3 Process for realising a connecting structure 审中-公开
标题翻译：一种用于获得结构的化合物的方法
公开(公告)号：EP2445000A3
公开(公告)日：2013-06-05
申请号：EP11290473.5
申请日：2011-10-13
申请人： Soitec
发明人： Landru, Didier
IPC分类号： H01L21/60 , H01L23/485 , H01L25/065
CPC分类号： H01L24/05 , H01L24/03 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0332 , H01L2224/034 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03616 , H01L2224/05006 , H01L2224/05082 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05186 , H01L2224/05187 , H01L2224/05546 , H01L2224/05547 , H01L2224/05576 , H01L2224/05578 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05681 , H01L2224/05687 , H01L2224/08121 , H01L2224/80203 , H01L2224/80357 , H01L2224/80895 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/15788 , H01L2924/00014 , H01L2924/04953 , H01L2924/05042 , H01L2924/04941 , H01L2924/00
摘要： The present invention relates to a process for realizing a connecting structure (2200) in a semiconductor substrate (1000), and the semiconductor substrate realized accordingly. The process of the present invention, the semiconductor substrate (1000) having at least a first surface, and being foreseen for a 3D integration with a second substrate (1700) along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value, can include the step of growing a diffusion barrier structure (2211) for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure (2211) being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure (2211) can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure (2211) is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate (1700) is prevented in the integrated state.

5. 发明授权

EP0610709B1 Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung 有权转让
标题翻译：维尔法赫恩·赫斯特伦
公开(公告)号：EP0610709B1
公开(公告)日：1998-06-10
申请号：EP94100990.4
申请日：1994-01-24
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Hubner, Holger, Dr
IPC分类号： H01L21/98 , H01L25/065 , H01L23/48
CPC分类号： H01L25/50 , H01L23/48 , H01L25/0657 , H01L2224/0401 , H01L2224/05009 , H01L2224/05547 , H01L2224/13022 , H01L2224/8384 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/01068 , H01L2924/01079

6. 发明公开

EP0610709A1 Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung 有权转让
标题翻译：维尔法赫恩·赫斯特伦
公开(公告)号：EP0610709A1
公开(公告)日：1994-08-17
申请号：EP94100990.4
申请日：1994-01-24
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Hubner, Holger, Dr
IPC分类号： H01L21/98 , H01L25/065 , H01L23/48
CPC分类号： H01L25/50 , H01L23/48 , H01L25/0657 , H01L2224/0401 , H01L2224/05009 , H01L2224/05547 , H01L2224/13022 , H01L2224/8384 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/01068 , H01L2924/01079
摘要： Zur Herstellung einer dreidimensionalen Schaltungsanordnung werden übereinander angeordnete Substrate (1a, 1b) durch mit einem Gemisch aus zwei Metallkomponenten, von denen die eine flüssig und die andere fest ist und von denen sich die feste Komponente in der flüssigen löst, was zur Aushärtung des Gemischs führt, gefüllte Vertiefungen (2a, 2b) in den aneinandergrenzenden Flächen der benachbarten Substrate (1a, 1b) durch Aushärten des Gemisches (7a, 7b) fest miteinander verbunden. Insbesondere werden vereinzelte Bauelemente auf vorbereiteten Substratscheiben angeordnet und mit diesen fest verbunden.
摘要翻译：为了制造三维电路装置，一个在另一个之上布置的基板（1a，1b）通过在相邻基板的表面中的凹部（2a，2b）彼此牢固地连接，该凹槽被填充，边界（1a，1b）与两种金属组分的混合物（其中一种是液体，另一种固体，其中固体组分溶解在液体中，导致混合物硬化），混合物（7a ，7b）。特别地，单个部件布置在准备的基板盘上并且牢固地连接到其上。

7. 发明授权

EP1438744B1 METHOD OF FORMING A RAISED CONTACT FOR A SUBSTRATE 有权
标题翻译：方法产生关于相关联系人在衬底
公开(公告)号：EP1438744B1
公开(公告)日：2014-01-29
申请号：EP03751773.7
申请日：2003-06-13
申请人： Intel Corporation
发明人： FISCHER, Paul , BOARDMAN, James , MILLER, Anne
IPC分类号： H01L21/321 , H01L21/768 , H01L23/00 , H01L23/485 , H01L25/065 , H01L23/532 , H01L23/522
CPC分类号： H01L21/3212 , H01L21/7684 , H01L23/5222 , H01L23/5329 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05547 , H01L2224/05572 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2224/80895 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/12 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： The present invention includes a method of providing a first substrate; forming an insulator over the first substrate; forming an opening in the insulator; forming a conductor over the insulator and in the opening; removing the conductor over the insulator with a first chemical-mechanical polish process to leave the conductor in the opening; and reducing thickness of the insulator with a second chemical-mechanical process to permit the conductor in the opening to protrude.The present invention further includes a structure having such a conductor that protrudes.

8. 发明公开

EP2466632A3 Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods 审中-公开
标题翻译：正在使用该方法形成于半导体结构的直接键合和键合的半导体结构的方法
公开(公告)号：EP2466632A3
公开(公告)日：2012-07-04
申请号：EP11193906.2
申请日：2011-12-16
申请人： Soitec
发明人： Sadaka, Mariam
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/06 , H01L25/50 , H01L2224/0346 , H01L2224/03602 , H01L2224/0361 , H01L2224/05006 , H01L2224/05026 , H01L2224/05147 , H01L2224/05541 , H01L2224/05547 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/05657 , H01L2224/05684 , H01L2224/05686 , H01L2224/08121 , H01L2224/08147 , H01L2224/08501 , H01L2224/0903 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/8383 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/14 , H01L2924/00012 , H01L2924/01014 , H01L2924/049 , H01L2924/01015 , H01L2924/206 , H01L2224/05552 , H01L2924/00
摘要： Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.

9. 发明公开

EP2445000A2 Process for realising a connecting structure 审中-公开
标题翻译： Verfahren zum Erhalt einer Verbindungsstruktur
公开(公告)号：EP2445000A2
公开(公告)日：2012-04-25
申请号：EP11290473.5
申请日：2011-10-13
申请人： Soitec
发明人： Landru, Didier
IPC分类号： H01L21/60 , H01L23/485 , H01L25/065
CPC分类号： H01L24/05 , H01L24/03 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0332 , H01L2224/034 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03616 , H01L2224/05006 , H01L2224/05082 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05186 , H01L2224/05187 , H01L2224/05546 , H01L2224/05547 , H01L2224/05576 , H01L2224/05578 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05681 , H01L2224/05687 , H01L2224/08121 , H01L2224/80203 , H01L2224/80357 , H01L2224/80895 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/15788 , H01L2924/00014 , H01L2924/04953 , H01L2924/05042 , H01L2924/04941 , H01L2924/00
摘要： The present invention relates to a process for realizing a connecting structure (2200) in a semiconductor substrate (1000), and the semiconductor substrate realized accordingly. The process of the present invention, the semiconductor substrate (1000) having at least a first surface, and being foreseen for a 3D integration with a second substrate (1700) along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value, can include the step of growing a diffusion barrier structure (2211) for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure (2211) being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure (2211) can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure (2211) is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate (1700) is prevented in the integrated state.
摘要翻译：本发明涉及一种在半导体衬底（1000）中实现连接结构（2200）的方法，并且相应地实现了半导体衬底。本发明的方法，半导体衬底（1000）具有至少第一表面，并且被预见用于沿着第一表面与第二衬底（3D）进行3D集成，其中3D集成受到横向错位具有不对准值的至少一个维度可以包括生长用于防止元件从导电层扩散到半导体衬底的其余部分中的扩散阻挡结构（2211）的步骤，其特征在于，第一端面是扩散阻挡结构（2211）的最外侧表面基本上平行于第一表面沿着垂直于第一表面的方向并且从衬底朝着第一表面延伸，扩散阻挡结构（2211）可以具有长度在横向偏移的方向上，长度取决于不对准值，其中扩散阻挡结构（2211）i的长度被选择为使得在3D集成结构中，在整合状态下防止元件从第二基板（1700）的导电层的扩散。

10. 发明公开

EP2099065A4 SEMICONDUCTOR DEVICE 审中-公开
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP2099065A4
公开(公告)日：2011-02-23
申请号：EP07850989
申请日：2007-12-20
申请人： ROHM CO LTD
发明人： KASAI MASAKI , OKUMURA HIROSHI
IPC分类号： H01L21/60
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05007 , H01L2224/05018 , H01L2224/05027 , H01L2224/05082 , H01L2224/05541 , H01L2224/05547 , H01L2224/05552 , H01L2224/05557 , H01L2224/05559 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13006 , H01L2224/13099 , H01L2224/131 , H01L2924/00014 , H01L2924/0002 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/19043 , H01L2924/207 , H01L2924/00
摘要： An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.
摘要翻译：本发明的半导体器件包括：半导体芯片; 设置在半导体芯片的表面上用于电连接的内部焊盘; 表面保护膜，其覆盖半导体芯片的表面并且具有焊盘开口，内部焊盘从所述焊盘开口露出; 应力消除层，设置在所述表面保护膜上并具有开口部分，从所述焊盘开口暴露的所述内部焊盘通过所述开口部分暴露; 连接垫，该连接垫包括埋设在焊盘开口和开口部分中并连接到内部焊盘的锚;以及突起，该突起与突起一体地设置并突出到应力消除层上，突起的宽度大于该开口的开口宽度开口部分; 以及用于外部电连接的金属球，以覆盖连接垫的突出部。

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