![Process for realising a connecting structure](/ep/2012/04/25/EP2445000A2/abs.jpg.150x150.jpg)
基本信息:
- 专利标题: Process for realising a connecting structure
- 专利标题(中):Verfahren zum Erhalt einer Verbindungsstruktur
- 申请号:EP11290473.5 申请日:2011-10-13
- 公开(公告)号:EP2445000A2 公开(公告)日:2012-04-25
- 发明人: Landru, Didier
- 申请人: Soitec
- 申请人地址: Chemin des Franques Parc Technologique des Fontaines 38190 Bernin FR
- 专利权人: Soitec
- 当前专利权人: Soitec
- 当前专利权人地址: Chemin des Franques Parc Technologique des Fontaines 38190 Bernin FR
- 代理机构: Grünecker, Kinkeldey, Stockmair & Schwanhäusser
- 优先权: FR1004050 20101014
- 主分类号: H01L21/60
- IPC分类号: H01L21/60 ; H01L23/485 ; H01L25/065
摘要:
The present invention relates to a process for realizing a connecting structure (2200) in a semiconductor substrate (1000), and the semiconductor substrate realized accordingly. The process of the present invention, the semiconductor substrate (1000) having at least a first surface, and being foreseen for a 3D integration with a second substrate (1700) along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value, can include the step of growing a diffusion barrier structure (2211) for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure (2211) being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure (2211) can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure (2211) is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate (1700) is prevented in the integrated state.
摘要(中):
本发明涉及一种在半导体衬底(1000)中实现连接结构(2200)的方法,并且相应地实现了半导体衬底。 本发明的方法,半导体衬底(1000)具有至少第一表面,并且被预见用于沿着第一表面与第二衬底(3D)进行3D集成,其中3D集成受到横向错位 具有不对准值的至少一个维度可以包括生长用于防止元件从导电层扩散到半导体衬底的其余部分中的扩散阻挡结构(2211)的步骤,其特征在于,第一端面是 扩散阻挡结构(2211)的最外侧表面基本上平行于第一表面沿着垂直于第一表面的方向并且从衬底朝着第一表面延伸,扩散阻挡结构(2211)可以具有长度 在横向偏移的方向上,长度取决于不对准值,其中扩散阻挡结构(2211)i的长度 被选择为使得在3D集成结构中,在整合状态下防止元件从第二基板(1700)的导电层的扩散。
公开/授权文献:
- EP2445000A3 Process for realising a connecting structure 公开/授权日:2013-06-05
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
--------H01L21/02 | .半导体器件或其部件的制造或处理 |
----------H01L21/027 | ..未在H01L21/18或H01L21/34组中包含的为进一步的光刻工艺在半导体之上制作掩膜 |
------------H01L21/50 | ...应用H01L21/06至H01L21/326中的任一小组都不包含的方法或设备组装半导体器件的 |
--------------H01L21/60 | ....引线或其他导电构件的连接,用于工作时向或由器件传导电流 |