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1. 发明授权

EP3153463B1 METHOD FOR PRODUCING A PILLAR STRUCTURE IN A SEMICONDUCTOR LAYER 有权
公开(公告)号：EP3153463B1
公开(公告)日：2018-06-13
申请号：EP15188985.4
申请日：2015-10-08
申请人： IMEC VZW
发明人： Chan, Boon Teik , Paraschiv, Vasile , Altamirano Sanchez, Efrain , Tao, Zheng
IPC分类号： H01L29/775 , H01L29/06 , H01L21/306 , H01L21/308 , B82Y10/00 , B82Y40/00
CPC分类号： H01L21/02603 , B82Y10/00 , B82Y40/00 , H01L21/265 , H01L21/28008 , H01L21/3065 , H01L21/3083 , H01L21/3085 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775
摘要： A method for producing a pillar structure (40) in a semiconductor layer, the method comprising providing a structure comprising, on a main surface, a semiconductor layer (30). A patterned hard mask layer stack (10, 20) is provided on the semiconductor layer that comprises a first layer (20) in contact with the semiconductor layer and a second layer (10) overlying and in contact with the first layer.The semiconductor layer is dry plasma etched using the patterned hard mask layer stack as a mask (Fig. 5(d-g)). The dry plasma etching comprises subjecting the structure to a first plasma (Fig. 5(d)) thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure (41), thereafter subjecting the structure to a second plasma (Fig. 5(f)) thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure (42). A height of the removed first part (41) is greater than a height of the removed second part (42).

2. 发明公开

EP3178112A4 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED BACK SIDE FEATURES 审中-公开
公开(公告)号：EP3178112A4
公开(公告)日：2018-05-16
申请号：EP15829962
申请日：2015-07-28
申请人： QUALCOMM INC
发明人： FANELLI STEPHEN A
IPC分类号： H01L27/12 , H01L21/265 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/266 , H01L21/28008 , H01L21/28176 , H01L21/31111 , H01L21/31116 , H01L21/31155 , H01L21/7624 , H01L21/84 , H01L23/367 , H01L29/42384 , H01L29/66772 , H01L29/7838 , H01L29/7843 , H01L29/7849 , H01L29/78603 , H01L29/78648 , H01L29/78654
摘要： Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.

3. 发明公开

EP3073522A4 ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE 有权
标题翻译： ARRAYSUBSTRAT UND HERSTELLUNGSVERFAHRENDAFÜRUND ANZEIGEVORRICHTUNG
公开(公告)号：EP3073522A4
公开(公告)日：2017-06-28
申请号：EP14859300
申请日：2014-07-25
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： LIU XIANG
IPC分类号： H01L27/12 , H01L21/027 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L29/49 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1288 , H01L21/02565 , H01L21/0274 , H01L21/28008 , H01L21/31144 , H01L21/32139 , H01L21/441 , H01L21/469 , H01L21/47573 , H01L21/47635 , H01L21/56 , H01L21/76831 , H01L23/3171 , H01L23/5226 , H01L23/528 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L27/127 , H01L29/24 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： An array substrate, a manufacturing method thereof, and a display device are provided, which are related to a display technology filed. The method includes: forming a pattern layer (201a) including a pixel electrode (20), and a pattern layer including a gate electrode (30) and a gate line on a base substrate (10) through one patterning process; on the substrate (10) with the pattern layer including the gate electrode (30) and the gate line formed thereon, forming a gate insulating layer (401), a pattern layer at least including a metal oxide semiconductor active layer (50) and a pattern layer at least including an etch stop layer (601) through one patterning process or two patterning processes; wherein, a first via hole (71) for exposing the pixel electrode (20) is formed over the pixel electrode (20); on the substrate (10) with the etch stop layer (601) formed thereon, forming a pattern layer including a source electrode (80a), a drain electrode (80b) and a data line through one patterning process; wherein, the source electrode (80a) and the drain electrode (80b) each contact a metal oxide semiconductor active layer (50), and the drain electrode (80a) is electrically connected to the pixel electrode (20) through the first via hole (71).
摘要翻译：提供了一种阵列基板及其制造方法和显示装置，与显示技术领域相关。该方法包括：通过一次构图工艺在衬底基板（10）上形成包括像素电极（20）的图形层（201a）以及包括栅电极（30）和栅线的图形层; 在具有包括栅极电极30和形成在其上的栅极线的图案层的衬底10上形成栅极绝缘层401，至少包括金属氧化物半导体活性层50和图案化层50的图案层，通过一个构图工艺或两个构图工艺至少包括蚀刻停止层（601）的图案层; 其中，在像素电极（20）上形成用于暴露像素电极（20）的第一通孔（71）; 在其上形成有蚀刻停止层（601）的衬底（10）上，通过一次构图工艺形成包括源电极（80a），漏电极（80b）和数据线的图形层; 其中，所述源电极80a和所述漏电极80b分别与金属氧化物半导体有源层50接触，所述漏电极80a通过所述第一过孔电连接所述像素电极20， 71）。

4. 发明公开

EP2937895A1 MANUFACTURING METHOD OF MULTI-GATE FIN FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES FELDEFFEKTTRANSISTERS MIT MEHRFACHGATE-RIPPEN
公开(公告)号：EP2937895A1
公开(公告)日：2015-10-28
申请号：EP14749414.0
申请日：2014-02-07
申请人： Huawei Technologies Co., Ltd.
发明人： ZHAO, Jing
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/28008
摘要： Embodiments of the present invention provide a method for producing a multi-gate fin field-effect transistor, including: forming a channel layer and a gate medium layer on a substrate; forming an amorphous silicon layer on the substrate, and etching the amorphous silicon layer by using an etching process, to form at least one fin; forming, by using an epitaxial growth process, a first protective layer from both sides to the middle of the substrate along a length direction of the at least one fin until a groove is formed in a middle location along the length direction of the at least one fin; forming a gate electrode layer on the substrate, performing planarization processing on the gate electrode layer to expose the first protective layer, and etching away the first protective layer by using an etching process, so as to form a gate electrode; and forming a source electrode and a drain electrode on the substrate. According to the embodiments of the present invention, a gate electrode of a FinFET is formed by using an epitaxial growth process and an etching process, so as to implement alignment of the gate electrode and a central location, of a fin, along a length direction, solve a problem of imbalance of series resistance between a drain electrode and a source electrode, and ensure component performance of the FinFET.
摘要翻译：本发明的实施例提供了一种制造多栅极鳍场效应晶体管的方法，包括：在衬底上形成沟道层和栅极介质层; 在所述基板上形成非晶硅层，并且通过使用蚀刻工艺蚀刻所述非晶硅层，以形成至少一个翅片; 通过使用外延生长工艺沿着所述至少一个翅片的长度方向形成从所述基板的两侧到所述中间的第一保护层，直到沿着所述至少一个翅片的长度方向在中间位置形成凹槽鳍; 在所述基板上形成栅极电极层，对所述栅极电极层进行平坦化处理，使所述第一保护层露出，利用蚀刻工序蚀刻所述第一保护层，形成栅电极; 以及在所述衬底上形成源电极和漏电极。根据本发明的实施例，通过使用外延生长工艺和蚀刻工艺来形成FinFET的栅电极，从而沿着长度方向实现鳍状物的栅电极和中心位置的对准解决了漏电极和源电极之间串联电阻不平衡的问题，并确保了FinFET的元件性能。

5. 发明公开

EP2449593A4 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译： HERSTELLUNGSVERFAHRENFÜRHALBLEITERBAUELEMENT
公开(公告)号：EP2449593A4
公开(公告)日：2015-06-03
申请号：EP10793992
申请日：2010-06-09
申请人： SEMICONDUCTOR ENERGY LAB
发明人： OIKAWA YOSHIAKI , OKAZAKI KENICHI , MARUYAMA HOTAKA
IPC分类号： H01L29/786 , H01L21/02 , H01L21/28 , H01L27/12 , H01L29/66
CPC分类号： H01L29/66969 , H01L21/02502 , H01L21/02565 , H01L21/02664 , H01L21/28008 , H01L27/1225 , H01L29/7869 , H01L29/78696
摘要： Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor.
摘要翻译：公开了一种制造具有氧化物半导体作为沟道形成区域的薄膜晶体管的方法。该方法包括：在栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成与所述氧化物半导体层接触的源电极层和漏极电极层，使得所述氧化物半导体层的至少一部分露出; 以及在氧化物半导体层上形成氧化物绝缘膜并与氧化物半导体层接触。在形成氧化物绝缘膜之前，氧化物半导体的暴露部分可能在存在等离子体的情况下暴露于含氧气体。该方法允许氧扩散到氧化物半导体层中，这有助于薄膜晶体管的优异特性。

6. 发明公开

EP2273538A3 Dielectric interface for group III-V semiconductor device 有权
标题翻译：电介质接口，用于一III-V族半导体器件
公开(公告)号：EP2273538A3
公开(公告)日：2011-03-02
申请号：EP10184650.9
申请日：2006-11-17
申请人： Intel Corporation
发明人： Brask, Justin, K , Datta, Suman , Doczy, Mark, L , Blackwell, James, M , Metz, Matthew, V , Kavalieros, Jack, T. , Chau, Robert, S
IPC分类号： H01L21/314 , H01L29/51 , H01L21/28 , H01L21/335 , H01L29/49 , H01L29/788 , H01L21/316 , H01L29/20
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

7. 发明公开

EP2273538A2 Dielectric interface for group III-V semiconductor device 有权
标题翻译： Dielektrische Schnittstellefüreine Gruppe III-V-Halbleitervorrichtung
公开(公告)号：EP2273538A2
公开(公告)日：2011-01-12
申请号：EP10184650.9
申请日：2006-11-17
申请人： Intel Corporation
发明人： Brask, Justin, K , Datta, Suman , Doczy, Mark, L , Blackwell, James, M , Metz, Matthew, V , Kavalieros, Jack, T. , Chau, Robert, S
IPC分类号： H01L21/314 , H01L29/51 , H01L21/28 , H01L21/335 , H01L29/49 , H01L29/788 , H01L21/316 , H01L29/20
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译：描述了III-V族半导体器件及其制造方法。高k电介质通过硫族化物区域连接到约束区域。

8. 发明公开

EP1338914A2 Method for manufacturing liquid crystal display 失效
标题翻译： Verfahren zur Herstellung vonFlüssigkristallanzeigevorrichtungen
公开(公告)号：EP1338914A2
公开(公告)日：2003-08-27
申请号：EP03076155.5
申请日：1996-11-19
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Lee, Jueng-gil, 107-103 Chungkoo Apt. , Nam, Hyo-rak, Ka-209 Sunghwan Villa , Lee, Jung-ho
IPC分类号： G02F1/1362
CPC分类号： G02F1/136286 , G02F1/1345 , G02F1/13458 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a liquid crystal display is provided. The method includes the steps of forming a gate electrode and a gate line on a substrate, wherein said gate electrode and said gate line comprises at least one refractory metal layer;

forming an insulating film on said gate electrode and said gate line;
forming an amorphous silicon film pattern and a doped amorphous silicon film pattern on said insulating film, wherein said doped amorphous silicon film pattern is formed entirely on said amorphous silicon film pattern and a whole bottom surface of said doped amorphous silicon film pattern is directly contacted to said amorphous silicon film pattern;
forming a source electrode and a drain electrode composed of a third metal film and then etching away a portion of said doped amorphous silicon film pattern located between said source electrode and said drain electrode;
forming a protection film pattern having a first contact hole which exposes a portion of said drain electrode and a second contact hole which exposes a portion of said gate line, wherein said protection film pattern contacts a top surface of said amorphous silicon pattern located between said source electrode and said drain electrode and said insulating film under said second contact hole is etched away to expose a portion of said gate line; and
forming a first pixel electrode pattern which is connected to said drain electrode through said first contact hole and a second pixel electrode pattern which is electrically connected to said gate line through said second contact hole. It is thus possible to reduce the number of photolithography processes and to prevent a battery effect and generation of a hillock.
摘要翻译：提供一种制造液晶显示器的方法。该方法包括在基板上形成栅电极和栅极线的步骤，其中所述栅电极和所述栅极线包括至少一个难熔金属层; 在所述栅电极和所述栅极线上形成绝缘膜; 在所述绝缘膜上形成非晶硅膜图案和掺杂非晶硅膜图案，其中所述掺杂非晶硅膜图案完全形成在所述非晶硅膜图案上，并且所述掺杂非晶硅膜图案的整个底表面直接接触所述非晶硅膜图案; 形成由第三金属膜构成的源电极和漏电极，然后蚀刻位于所述源电极和所述漏电极之间的所述掺杂非晶硅膜图案的一部分; 形成具有暴露所述漏电极的一部分的第一接触孔和暴露所述栅极线的一部分的第二接触孔的保护膜图案，其中所述保护膜图案接触位于所述源极之间的所述非晶硅图案的顶表面电极和所述漏电极和所述第二接触孔下面的所述绝缘膜被蚀刻掉以露出所述栅极线的一部分; 以及形成通过所述第一接触孔连接到所述漏电极的第一像素电极图案和通过所述第二接触孔电连接到所述栅极线的第二像素电极图案。因此，可以减少光刻工艺的数量并防止电池效应和产生小丘。

9. 发明授权

EP1008893B1 ACTIVE MATRIX LIQUID CRYSTAL DISPLAY 失效
标题翻译：有源矩阵液晶显示器
公开(公告)号：EP1008893B1
公开(公告)日：2003-04-09
申请号：EP96939310.7
申请日：1996-11-27
申请人： Hitachi, Ltd.
发明人： ANDO, Masahiko , WAKAGI, Masatoshi , FUKAYA, Ritsuo
IPC分类号： G02F1/136 , G02F1/1333 , G02F1/133 , G02F1/1343
CPC分类号： G02F1/1368 , G02F1/134363 , H01L21/28008 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/66765 , H01L29/78669
摘要： A thin film transistor used as a switching element of an active matrix liquid crystal display is an enhancement-mode thin film transistor including a silicon nitride film (13) formed over a scanning electrode (12), an insulating layer (14) formed over the silicon nitride film (13), and a semiconductor layer having a source region (17) and a drain region (18) formed over the insulating layer (14). The thin film transistor has a threshold voltage higher than the maximum of the liquid crystal operating voltage. The insulating layer (14) is a silicon oxide film having a thickness of 30 angstroms or more.

10. 发明公开

EP0775931A3 Method for manufacturing liquid crystal display 失效
标题翻译： Verfahren zur Herstellung einerFlüssigkristall-Anzeige
公开(公告)号：EP0775931A3
公开(公告)日：1998-03-25
申请号：EP96308344.9
申请日：1996-11-19
申请人： Samsung Electronics Co., Ltd.
发明人： Lee, Jueng-gil , Lee, Jung-ho , Nam, Hyo-rak
IPC分类号： G02F1/136
CPC分类号： G02F1/136286 , G02F1/1345 , G02F1/13458 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L21/28008 , H01L23/4827 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/42384 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a liquid crystal display is provided. The method includes the steps of forming a gate electrode and a gate pad by sequentially depositing a first metal film (22) and a second metal film (24) on a substrate (20) on a thin film transistor (TFT) area and a pad area, respectively, by a first photolithography process, forming an insulating film (26) on the entire surface of the substrate (20) on which the gate electrode and the gate pad are formed, forming a semiconductor film pattern (28,30) on the insulating film (26) of the TFT area using a second photolithography process, forming a source electrode (32a) and a drain electrode (32b) composed of a third metal film in the TFT area using a third photolithography process, forming a protection film pattern (34) which exposes a portion of the drain electrode (32b) and a portion of the gate pad on the substrate on which the source electrode (32a) and the drain electrode (32b) are formed using a fourth photolithography process, and forming a pixel electrode (36) connected to the drain electrode and the gate pad on the substrate on which the protection film pattern is formed using a fifth photolithography process. It is thus possible to reduce the number of photolithography processes and to prevent a battery effect and generation of a hillock.
摘要翻译：提供一种制造液晶显示器的方法。该方法包括在基板上形成栅电极和栅极线的步骤，其中所述栅电极和所述栅极线包括至少一个难熔金属层; 在所述栅电极和所述栅极线上形成绝缘膜; 在所述绝缘膜上形成非晶硅膜图案和掺杂非晶硅膜图案，其中所述掺杂非晶硅膜图案完全形成在所述非晶硅膜图案上，并且所述掺杂非晶硅膜图案的整个底表面直接接触所述非晶硅膜图案; 形成由第三金属膜构成的源电极和漏电极，然后蚀刻位于所述源电极和所述漏电极之间的所述掺杂非晶硅膜图案的一部分; 形成具有暴露所述漏电极的一部分的第一接触孔和暴露所述栅极线的一部分的第二接触孔的保护膜图案，其中所述保护膜图案接触位于所述源极之间的所述非晶硅图案的顶表面电极和所述漏电极和所述第二接触孔下面的所述绝缘膜被蚀刻掉以露出所述栅极线的一部分; 以及形成通过所述第一接触孔连接到所述漏电极的第一像素电极图案和通过所述第二接触孔电连接到所述栅极线的第二像素电极图案。因此，可以减少光刻工艺的数量并防止电池效应和产生小丘。

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