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1. 发明授权

EP0091815B1 Static-type semiconductor memory device 失效
标题翻译：静态型半导体存储器件
公开(公告)号：EP0091815B1
公开(公告)日：1989-01-11
申请号：EP83302037.3
申请日：1983-04-12
申请人： FUJITSU LIMITED
发明人： Kimoto, Masayoshi
IPC分类号： G11C11/40 , G11C5/00
CPC分类号： G11C5/005 , G11C11/414 , G11C11/416

2. 发明公开

EP0037734A2 Semiconductor memory chip, and a memory device including such chips 失效
标题翻译： Halbleiterspeicherbaustein und Speicheranordnung mit solchen Bausteinen。
公开(公告)号：EP0037734A2
公开(公告)日：1981-10-14
申请号：EP81301494.1
申请日：1981-04-07
申请人： FUJITSU LIMITED
发明人： Yamada, Katsuyuki , Isogai, Hideaki
IPC分类号： G11C11/40 , G11C7/00
CPC分类号： G11C11/414
摘要： Circuitry is provided for clamping bit line voltage, when a chip is non-selected, to a level (RL) higher than the bit line voltage level (R) during read operation when the chip is selected.
For example, data lines D, D, which carry read voltage R in a read operation when the chip is selected, are connected to the bases of read transistors 0, o , Q 11 which are connected in turn to bit lines Boo, B 01 ; B 10 , B 11 .
A clamp circuit CL is connected to the lines D, D. The clamp circuit has a multi-emitter transistor Q 8 , emitters of which are connected to the data lines D, D. The collector of Q 8 is connected to power supply line V DD , and the base is connected to a circuit point P 1 which is high level when the chip is non-selected, and low level when the chip is selected. When P, is high level transistor Q 8 is turned ON and a high level voltage Voo - V BE is applied to the data lines D, D to clamp the bit line voltage to RL. (VSE is the base-emitter potential of Q a ).
摘要翻译：提供电路，用于当芯片未被选择时将位线电压钳位到高于选择芯片的读取操作期间的位线电压电平（R）的电平（RL）。例如，当选择芯片时，在读取操作中携带读取电压R的数据线D，D连接到依次连接到位线B00的读取晶体管Q10，Q11的基极; B01 B10，B11。钳位电路CL连接到线路D，D。钳位电路具有多发射极晶体管Q8，其发射极连接到数据线D，D。Q8的集电极连接到电源电源线VDD，并且基极连接到当芯片未被选择时为高电平的电路点P1，并且当选择芯片时，基极连接到低电平。当P1是高电平晶体管Q8导通时，高电平电压VDD-VBE被施加到数据线D，D以将位线电压钳位到RL。（VBE是Q8的基极 - 发射极电位）。

3. 发明公开

EP0181819A3 Memory cell power scavenging apparatus and method 失效
标题翻译：存储单元电源扫描装置和方法
公开(公告)号：EP0181819A3
公开(公告)日：1988-06-08
申请号：EP85402151
申请日：1985-11-07
申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
发明人： Herndon, William H.
IPC分类号： G11C05/00 , G11C08/00 , G11C11/40
CPC分类号： G11C5/14 , G11C8/08 , G11C11/414
摘要： The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required to maintain the memory cell in a preset state flows from the U cc source through a row of parallel memory cells and through a common bias supply and various peripheral circuits, such as decoders. A shunt voltage regulator controls the dependence of the common bias supply voltage on current fluctuations caused by addressing and deaddressing the memory cells. The invention includes an isolation device for isolating a particular row of memory cells when it is addressed without disturbing the bias on other memory cell rows. Similarly, the reference voltages of each of the peripheral circuits can be made independent of the common bias supply voltage and independent of the other peripheral circuits by the use of a local voltage regulator on each peripheral.

4. 发明授权

EP0037734B1 SEMICONDUCTOR MEMORY CHIP, AND A MEMORY DEVICE INCLUDING SUCH CHIPS 失效
标题翻译：半导体存储器芯片，以及包括这些芯片的存储器件
公开(公告)号：EP0037734B1
公开(公告)日：1986-12-30
申请号：EP81301494
申请日：1981-04-07
申请人： FUJITSU LIMITED
发明人： YAMADA, KATSUYUKI , ISOGAI, HIDEAKI
IPC分类号： G11C11/413 , G11C11/414 , G11C11/40 , G11C7/00
CPC分类号： G11C11/414

5. 发明授权

EP0016827B1 HIGH DENSITY MEMORY SYSTEM 失效
标题翻译：高密度记忆体系统
公开(公告)号：EP0016827B1
公开(公告)日：1984-12-05
申请号：EP79901181.2
申请日：1979-08-28
申请人： NCR CORPORATION
发明人： WARD, William Pearson
IPC分类号： G11C13/00
CPC分类号： G11C11/414 , G06F13/4243 , G11C7/22 , G11C11/409 , Y02D10/14 , Y02D10/151
摘要： A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into selected memory elements on one function conductor while eliminating the need for additional control conductors by causing the state of the signal on a clock conductor as compared to the state of the signal on the function conductor at selected times to control the operating mode of the memory system.
摘要翻译：高密度存储器系统包括多个可寻址电路板（201至202）。每个板包括一对芯片阵列（22），每个芯片阵列（22）包括成组布置的多个存储元件（56）。每个存储器元件（56）是包括多个存储环路的电荷耦合器件。在操作中，地址线（32）上的地址信号使与所选阵列（22）相关联的解码器（28）向包括多个单独时钟驱动器（241至24n）的时钟驱动器装置（24）提供比较信号，其中一个由行地址信号选择，由此提供改变的时钟脉冲宽度信号，该信号检测到该改变，从而启用一组存储元件（56）。功能驱动器电路（26）提供模式控制信号，其将使能的存储器元件（56）置于读取或写入操作模式。高密度存储系统的实现是因为只使用少量的电互连导体。

6. 发明公开

EP0037734A3 Semiconductor memory chip, and a memory device including such chips 失效
标题翻译：半导体存储器芯片，以及包括这样的芯片的存储器件
公开(公告)号：EP0037734A3
公开(公告)日：1983-06-29
申请号：EP81301494
申请日：1981-04-07
申请人： FUJITSU LIMITED
发明人： Yamada, Katsuyuki , Isogai, Hideaki
IPC分类号： G11C11/40 , G11C07/00
CPC分类号： G11C11/414
摘要： Circuitry is provided for clamping bit line voltage, when a chip is non-selected, to a level (RL) higher than the bit line voltage level (R) during read operation when the chip is selected. For example, data lines D, D, which carry read voltage R in a read operation when the chip is selected, are connected to the bases of read transistors 0, o , Q 11 which are connected in turn to bit lines Boo, B 01 ; B 10 , B 11 . A clamp circuit CL is connected to the lines D, D. The clamp circuit has a multi-emitter transistor Q 8 , emitters of which are connected to the data lines D, D. The collector of Q 8 is connected to power supply line V DD , and the base is connected to a circuit point P 1 which is high level when the chip is non-selected, and low level when the chip is selected. When P, is high level transistor Q 8 is turned ON and a high level voltage Voo - V BE is applied to the data lines D, D to clamp the bit line voltage to RL. (VSE is the base-emitter potential of Q a ).

7. 发明公开

EP0058845A3 Random access memory cell 失效
标题翻译：随机存取存储器
公开(公告)号：EP0058845A3
公开(公告)日：1986-03-19
申请号：EP82100719
申请日：1982-02-02
申请人： International Business Machines Corporation
发明人： Denis, Bernard Albert , Eardley, David Barry
IPC分类号： G11C11/40
CPC分类号： H01L27/1025 , G11C11/411 , G11C11/4116 , G11C11/414 , H03K3/288
摘要： Two memory cells each can be entirely fabricated in only two isolation beds. In one embodiment each bed contains one lateral PNP (64, 66) and one vertical NPN transistor (60, 62) in a merged structure. In a second embodiment, each bed contains one lateral PNP (118, 120) and two vertical NPN transistors (110, 122; 112, 124) in a merged structure. Memory access circuitry provides a high ratio of selected to unselected cell current in order to permit fast memory operation.

8. 发明授权

EP0022930B1 Nachladeschaltung für einen Halbleiterspeicher 失效
标题翻译：用于半导体存储器的充电电路
公开(公告)号：EP0022930B1
公开(公告)日：1984-06-13
申请号：EP80103389.5
申请日：1980-06-18
申请人： International Business Machines Corporation
发明人： Heuber, Klaus , Wiedmann, Siegfried, Dr.
IPC分类号： G11C7/00 , G11C11/40 , G05F3/20
CPC分类号： G05F3/22 , G11C11/4026 , G11C11/4113 , G11C11/414 , G11C11/416

9. 发明公开

EP0016827A4 HIGH DENSITY MEMORY SYSTEM. 失效
标题翻译：高密度存储系统。
公开(公告)号：EP0016827A4
公开(公告)日：1981-10-27
申请号：EP79901181
申请日：1980-04-08
申请人： NCR CORP
发明人： WARD WILLIAM PEARSON
IPC分类号： G11C7/00 , G06F13/42 , G11C7/22 , G11C11/34 , G11C11/401 , G11C11/409 , G11C11/414 , G11C27/00 , G11C13/00
CPC分类号： G11C11/414 , G06F13/4243 , G11C7/22 , G11C11/409 , Y02D10/14 , Y02D10/151
摘要： A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into selected memory elements on one function conductor while eliminating the need for additional control conductors by causing the state of the signal on a clock conductor as compared to the state of the signal on the function conductor at selected times to control the operating mode of the memory system.

10. 发明公开

EP0012663A1 Dispositif de réduction du temps d'accès aux informations contenues dans une mémoire d'un système de traitement de l'information 无效
标题翻译：为减少了访问时间的信息的数据处理系统的装置。
公开(公告)号：EP0012663A1
公开(公告)日：1980-06-25
申请号：EP79400956.3
申请日：1979-12-04
申请人： COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB)
发明人： Girard, Paul, Marie
IPC分类号： G11C11/40 , G11C11/24 , G11C11/34
CPC分类号： G11C7/106 , G11C7/1051 , G11C11/4093 , G11C11/414
摘要： Le dispositiv se compose d'un registre d'informations (2) dont l'entrée et la sortie sont reliées entre elles et à la sortie d'information de la mémoire (1) du système de traitement, la sortie du registre d'information (2) pouvant être connectée ou non à un organe d'emission (3).
Application: Système de traitement de données.

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