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1. 发明公开

EP2353097A1 STORAGE ARRAY TILE SUPPORTING SYSTOLIC MOVEMENT OPERATIONS 审中-公开
标题翻译：斯特拉斯堡大学教授
公开(公告)号：EP2353097A1
公开(公告)日：2011-08-10
申请号：EP09784055.7
申请日：2009-11-10
申请人： International Business Machines Corporation
发明人： STRUMPEN, Volker , FRIGO, Matteo
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0855 , G06F2212/271
摘要： A tile for use in a tiled storage array provides re-organization of values within the tile array without requiring sophisticated global control. The tiles operate to move a requested value to a front-most storage element of the tile array according to a global systolic clock. The previous occupant of the front-most location is moved or swapped backward according to the systolic clock, and the new occupant is moved forward according to the systolic clock, according to the operation of the tiles, while providing for multiple in-flight access requests within the tile array. The placement heuristic that moves the values is determined according to the position of the tiles within the array and the behavior of the tiles. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the tile array.
摘要翻译：用于平铺存储阵列的瓦片可以重新组织瓦片阵列中的值，而不需要复杂的全局控制。瓦片用于根据全局收缩时钟将请求的值移动到瓦片阵列的最前面的存储元件。根据收视时钟，最前面的位置的先前乘客向后移动或倒换，并且根据瓦片的操作根据收缩时钟向前移动新乘员，同时提供多个飞行中访问请求在瓷砖阵列内。根据数组中瓦片的位置和瓦片的行为来确定移动值的放置启发式。值的移动可以仅通过瓦片阵列内的相邻瓦片的下一个相邻连接来执行。

2. 发明公开

EP2353096A1 SPIRAL CACHE POWER MANAGEMENT, ADAPTIVE SIZING AND INTERFACE OPERATIONS 审中-公开
标题翻译：螺旋高速缓存电源管理，以及自适应测量接口操作
公开(公告)号：EP2353096A1
公开(公告)日：2011-08-10
申请号：EP09755875.3
申请日：2009-11-10
申请人： International Business Machines Corporation
发明人： STRUMPEN, Volker , FRIGO, Matteo
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/123 , G06F2212/1028 , G06F2212/271 , G06F2212/601 , Y02D10/13
摘要： A spiral cache memory provides low access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most storage tile of the spiral. If the spiral cache needs to eject a value to make space for a value moved to the front-most tile, space is made by ejecting a value from the cache to a backing store. A buffer along with flow control logic is used to prevent overflow of writes of ejected values to the generally slow backing store. The tiles in the spiral cache may be single storage locations or be organized as some form of cache memory such as direct-mapped or set-associative caches. Power consumption of the spiral cache can be reduced by dividing the cache into an active and inactive partition, which can be adjusted on a per-tile basis. Tile-generated or global power-down decisions can set the size of the partitions.

3. 发明公开

EP2975520A1 INFORMATION PROCESSING DEVICE, CONTROL METHOD OF INFORMATION PROCESSING DEVICE AND CONTROL PROGRAM OF INFORMATION PROCESSING DEVICE 审中-公开
标题翻译：信息处理装置，控制方法，用于信息处理设备，信息处理设备和控制程序
公开(公告)号：EP2975520A1
公开(公告)日：2016-01-20
申请号：EP15167947.9
申请日：2015-05-18
申请人： FUJITSU LIMITED
发明人： OTAWA, Tomohito
IPC分类号： G06F9/54
CPC分类号： G06F12/0815 , G06F9/54 , G06F9/543 , G06F12/0804 , G06F12/0868 , G06F12/0873 , G06F2212/2542 , G06F2212/271 , G06F2212/283
摘要： An information processing device comprising a plurality of nodes, each nodes comprising an arithmetic operation device configured to execute an arithmetic process, and a main memory which stores data, wherein each of arithmetic operation devices belonging to each of the plurality of nodes is configured to read a target data of which the arithmetic operation unit executes the arithmetic operation from a storage device except the main memory, based on a first address information indicating a storage position in the storage device, and write the target data into the main memory of own node.
摘要翻译：包括节点的一个多元化的信息处理设备中，每个节点包括运算装置的配置成在运算处理执行，并且存储数据，worin每个属于每个节点的多个算术运算设备的主存储器被配置为读取哪个的算术运算单元从存储设备执行算术运算以外的主存储器，基于第一地址信息，其指示在所述存储设备中的存储位置，并且目标数据写入到自己节点的主存储器中的目标数据。

4. 发明公开

EP2478441A1 READ AND WRITE AWARE CACHE 有权
标题翻译：阅读和写作有意识的BUFFER
公开(公告)号：EP2478441A1
公开(公告)日：2012-07-25
申请号：EP10749847.9
申请日：2010-08-31
申请人： International Business Machines Corporation
发明人： LI, Jian , RAJAMONY, Ramakrishnan , SPEIGHT, William Evan , ZHANG, Lixin
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

5. 发明公开

EP2227749A2 BUS ENHANCED NETWORK ON CHIP 有权
标题翻译： BUSERWEITERTES片上网络
公开(公告)号：EP2227749A2
公开(公告)日：2010-09-15
申请号：EP08856957.9
申请日：2008-12-07
申请人： Technion Research & Development Foundation Ltd.
发明人： CIDON, Israel , KOLODNY, Avinoam , WALTER, (Zigmond) Isask'har
IPC分类号： G06F15/78
CPC分类号： G06F15/7825 , G06F2212/271
摘要： A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.

6. 发明公开

EP2441005A2 SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：系统和方法缓冲器，以便在多核心处理器
公开(公告)号：EP2441005A2
公开(公告)日：2012-04-18
申请号：EP10734026.7
申请日：2010-06-09
申请人： Vorbach, Martin
发明人： VORBACH, Martin
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/526 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F12/0842 , G06F12/0893 , G06F2212/271 , G06F2212/50 , G06F2212/62 , Y02D10/13
摘要： The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

7. 发明公开

EP2353094A1 TILED STORAGE ARRAY WITH SYSTOLIC MOVE-TO-FRONT REORGANIZATION 有权
标题翻译：美国麻省理工学院麻省理工学院BEWEGUNG-NACH-VORNE-UMORGANISATION
公开(公告)号：EP2353094A1
公开(公告)日：2011-08-10
申请号：EP09747867.1
申请日：2009-11-10
申请人： International Business Machines Corporation
发明人： STRUMPEN, Volker , FRIGO, Matteo
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F3/0689 , G06F12/0897 , G06F12/123 , G06F2212/271
摘要： A tiled storage array provides reduction in access latency for frequently-accessed values by re-organizing to always move a requested value to a front-most storage element of array. The previous occupant of the front-most location is moved backward according to a systolic pulse, and the new occupant is moved forward according to the systolic pulse, preserving the uniqueness of the stored values within the array, and providing for multiple in-flight access requests within the array. The placement heuristic that moves the values according to the systolic pulse can be implemented by control logic within identical tiles, so that the placement heuristic moves the values according to the position of the tiles within the array. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the array.
摘要翻译：平铺的存储阵列通过重新组织来减少频繁访问的值的访问延迟，以便始终将请求的值移动到阵列的最前面的存储元素。根据收缩期脉搏，最前面的位置的前乘客向后移动，并且根据收缩脉冲向前移动新乘客，保持阵列内存储的值的唯一性，并提供多个飞行中访问数组内的请求。根据收缩脉冲移动值的放置启发式可以由相同的瓦片内的控制逻辑来实现，使得放置启发式根据阵列内的瓦片的位置来移动值。值的移动可以仅通过阵列内的相邻瓦片的下一邻居连接来执行。

8. 发明授权

EP2353094B1 TILED STORAGE ARRAY WITH SYSTOLIC MOVE-TO-FRONT REORGANIZATION 有权
标题翻译：倾斜式存储阵列，具有可移动的前后重组
公开(公告)号：EP2353094B1
公开(公告)日：2017-07-05
申请号：EP09747867.1
申请日：2009-11-10
申请人： International Business Machines Corporation
发明人： STRUMPEN, Volker , FRIGO, Matteo
IPC分类号： G06F12/0811 , G06F3/06 , G06F12/0897 , G06F12/123
CPC分类号： G06F12/0811 , G06F3/0689 , G06F12/0897 , G06F12/123 , G06F2212/271

9. 发明授权

EP2227749B1 BUS ENHANCED NETWORK ON CHIP 有权
标题翻译： BUSERWEITERTES片上网络
公开(公告)号：EP2227749B1
公开(公告)日：2014-08-27
申请号：EP08856957.9
申请日：2008-12-07
申请人： Technion Research & Development Foundation Ltd.
发明人： CIDON, Israel , KOLODNY, Avinoam , WALTER, (Zigmond) Isask'har
IPC分类号： G06F15/78
CPC分类号： G06F15/7825 , G06F2212/271

10. 发明授权

EP2478441B1 READ AND WRITE AWARE CACHE 有权
标题翻译：阅读和写作有意识的BUFFER
公开(公告)号：EP2478441B1
公开(公告)日：2014-02-26
申请号：EP10749847.9
申请日：2010-08-31
申请人： International Business Machines Corporation
发明人： LI, Jian , RAJAMONY, Ramakrishnan , SPEIGHT, William Evan , ZHANG, Lixin
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement policy. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is placed in one of the closer banks. The size ratio between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.

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