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1. 发明公开

EP3161615A1 IMPLEMENTATION FOR A HIGH PERFORMANCE BCD DIVIDER 无效
标题翻译：高性能BCD分割器的实现
公开(公告)号：EP3161615A1
公开(公告)日：2017-05-03
申请号：EP15739111.1
申请日：2015-06-27
申请人： Oracle International Corporation
发明人： OLSON, Christopher, H. , BROOKS, Jeffrey, S. , DANYSH, Albert
IPC分类号： G06F7/491 , G06F7/535
CPC分类号： G06F9/3001 , G06F7/4917 , G06F9/30014 , G06F9/30025 , G06F9/30029 , G06F9/3802 , G06F2207/4912 , G06F2207/5354
摘要： Embodiments of an apparatus are disclosed for performing arithmetic operations on provided operands. The apparatus may include a fetch unit, and an arithmetic logic unit (ALU). The fetch unit may be configured to retrieve two operands responsive to receiving an instruction, wherein the operands include binary-coded decimal values. The ALU may be configured to scale a value of each of the operands, and then compress the scaled values of the operands. The compressed values of the operands may include fewer data bits than the corresponding scaled values. The ALU may be further configured to estimate a portion of a result of the operation dependent upon the compressed values of the operands.
摘要翻译：公开了用于对所提供的操作数执行算术运算的装置的实施例。该装置可以包括提取单元和算术逻辑单元（ALU）。提取单元可以被配置为响应于接收指令来检索两个操作数，其中操作数包括二进制编码的十进制值。 ALU可以被配置为缩放每个操作数的值，然后压缩操作数的缩放值。操作数的压缩值可以包括比对应的缩放值更少的数据位。 ALU可以进一步被配置为根据操作数的压缩值来估计操作结果的一部分。

2. 发明公开

EP1275043A1 PERFORMING CALCULATION IN DIGITAL SIGNAL PROCESSING EQUIPMENT 审中-公开
标题翻译：计算中的数字信号处理设备导入
公开(公告)号：EP1275043A1
公开(公告)日：2003-01-15
申请号：EP01909874.8
申请日：2001-02-16
申请人： Nokia Corporation
发明人： PARVIAINEN, Jari, A.
IPC分类号： G06F7/552
CPC分类号： G06F7/535 , G06F1/035 , G06F7/5525 , G06F2101/08 , G06F2101/12 , G06F2207/5354
摘要： The invention relates to a method and digital signal processing equipment for performing a digital signal processing calculation, the method employing a look-up table (100) in which predetermined numerical values, which are inverse values of square roots of numbers, have been stored. In the method, the look-up table is searched (200) for the inverse value of the square root of a desired number. If the value in question is found in the look-up table, it is retrieved. If the value in question is not found in the look-up table, the number is scaled (202) such that the inverse value of the square root of the scaled number is found in the look-up table. The found value is then retrieved from the look-up table and descaled (206) to produce the inverse value of the square root of the number. The inverse value of the square root of the number is used to carry out a calculation (208).

3. 发明授权

EP0448448B1 Procédé pour calculer l'inverse d'un nombre et calculateur pour la mise en oeuvre dudit procédé 失效
标题翻译：的方法来计算一个数字和机器的倒数用于实施该方法
公开(公告)号：EP0448448B1
公开(公告)日：1998-01-14
申请号：EP91400700.0
申请日：1991-03-14
申请人： BULL S.A.
发明人： Keryvel, Georges , Thomas, Jean-Louis
IPC分类号： G06F7/52
CPC分类号： G06F1/0356 , G06F7/535 , G06F2101/12 , G06F2207/5354 , G06F2207/5355 , G06F2207/5356

4. 发明公开

EP1391812A1 Hardware accelerator for performing division 审中-公开
标题翻译： Hardwarebeschleuniger zurDurchführungvon分部手续
公开(公告)号：EP1391812A1
公开(公告)日：2004-02-25
申请号：EP02292060.7
申请日：2002-08-20
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Giacalone, Jean-Pierre
IPC分类号： G06F9/38 , G06F7/52
CPC分类号： G06F7/535 , G06F9/3877 , G06F2207/5354
摘要： An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.
摘要翻译：一种用于允许数据处理系统中的数字信号处理器（DSP）执行高速分割操作的装置和方法。在本发明的一个实施例中，在不超过两个周期内执行除法运算。在本发明的另一个实施例中，分割操作是分数格式。数据处理装置包括随机存取存储器，处理器（12,168）以及将所述随机存取存储器（104）耦合到所述处理器的接口（102），所述接口实现与所述处理器相关联的高速分割操作。本发明的接口还可以与双处理器或协处理器系统组合以增加数据处理效率。

5. 发明公开

EP0631228A1 Accurate digital divider 失效
标题翻译： Genaues数字化Divisionswerk。
公开(公告)号：EP0631228A1
公开(公告)日：1994-12-28
申请号：EP94304389.3
申请日：1994-06-17
申请人： QUESTECH LIMITED
发明人： Billing, Robert
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/49973 , G06F2207/5354 , G06F2207/5356
摘要： A digital divider (2,3) for forming the quotient (Q) of two numbers (A,B) includes means (4,5) providing values (Q + 1, Q - 1) of the quotient with possible rounding errors added to or subtracted therefrom. Selector switching means (7) is arranged to select one of the values (Q, Q + 1, Q - 1) under the control of a logic circuit operating according to the following rules.
摘要翻译：用于形成两个数字（A，B）的商（Q）的数字除法器（2,3）包括提供商的值（Q + 1，Q-1）的装置（4,5），其中可能的舍入误差被添加到或从其中减去。选择器切换装置（7）被布置为在根据以下规则操作的逻辑电路的控制下选择值（Q，Q + 1，Q-1）中的一个。

6. 发明公开

EP0466814A4 INTEGER DIVIDER CIRCUIT 失效
标题翻译：整数分频器电路
公开(公告)号：EP0466814A4
公开(公告)日：1993-02-24
申请号：EP90906531
申请日：1990-04-02
申请人： MOTOROLA INC.
发明人： OOMS, WILLIAM, J. , LEITCH, CLIFFORD, D. , DELGADO, RENE, M.
IPC分类号： G06F1/03 , G06F7/52 , G06F7/533 , G06F7/535
CPC分类号： G06F7/535 , G06F1/03 , G06F2207/5354 , G06F2207/5356
摘要： A divider circuit (100) for producing a quotient result (Q) within one cycle time is provided. The invention utilizes combinational circuitry for performing a division operation by computing a scaled reciprocal of the denominator (SRD) and multiplying the scaled output by a similarly scaled numerator. The denominator is scaled such that it falls within a predetermined range, and the reciprocal value may be looked up from a memory device such as a ROM (500). The output of the multiplier (SQ) may also be scaled in order to produce the desired result (Q). The resulting quotient has a controlled error over a wide range of numerator and denominator input values.

7. 发明授权

EP0111587B1 Method and apparatus for division operations 失效
标题翻译：分类操作的方法和装置
公开(公告)号：EP0111587B1
公开(公告)日：1986-11-05
申请号：EP82111929.4
申请日：1982-12-23
申请人： International Business Machines Corporation
发明人： Chevillat, Pierre, Dr. , Maiwald, Dietrich, Dr.
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5354

8. 发明公开

EP0149248A3 Method and apparatus for division using interpolation approximation 失效
标题翻译：使用插值逼近的方法和装置
公开(公告)号：EP0149248A3
公开(公告)日：1986-06-25
申请号：EP84116428
申请日：1984-12-28
申请人： HITACHI, LTD.
发明人： Nakano, Hiraku
IPC分类号： G06F07/52
CPC分类号： G06F7/535 , G06F1/0356 , G06F2101/12 , G06F2207/5351 , G06F2207/5352 , G06F2207/5354 , G06F2207/5356
摘要： A divide method and a divide apparatus are disclosed for use in a data processing system. The divisor and dividend are normalized in a normalization circuit (14). A table unit (8, 9, 17) stores a plurality of approximate reciprocal divisors and differences between adjacent approximate reciprocal divisors and is addressed by the high-order bits of the normalized divisor. The approximate reciprocal divisor read out from the table unit is, in an interpolation approximation circuit (18), changed into an interpolation approximated approximate reciprocal divisor in accordance with a plurality of bits following the high-order bits and the difference. A multiplication unit (19) multiplies the interpolation approximated approximate reciprocal divisor by the normalized dividend to output a quotient.

9. 发明公开

EP1421471A1 METHOD AND APPARATUS FOR EXECUTING DIVISION 审中-公开
标题翻译：方法和装置除法完成
公开(公告)号：EP1421471A1
公开(公告)日：2004-05-26
申请号：EP02748905.3
申请日：2002-08-06
申请人： Nokia Corporation
发明人： VIHRIÄLÄ, Jaakko
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F1/03 , G06F2101/12 , G06F2207/5354 , G06F2207/5356
摘要： The invention relates to a method and an electronic apparatus implementing the method of executing division. In the method, an auxiliary divisor is retrieved from a look-up table stored in the electronic apparatus, the auxiliary divisor being a predetermined number generated by the product of the powers of the integer two and the reciprocal of the divisor. In the method, the division is executed in the electronic apparatus by multiplying the dividend of the division by the auxiliary divisor. The result of the division is scaled in the electronic apparatus in order to represent it in the desired form by shifting the result obtained by multiplying.

10. 发明授权

EP0631228B1 Accurate digital divider 失效
标题翻译：精确的数字部门工作
公开(公告)号：EP0631228B1
公开(公告)日：2000-02-02
申请号：EP94304389.3
申请日：1994-06-17
申请人： QUESTECH LIMITED
发明人： Billing, Robert
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/49973 , G06F2207/5354 , G06F2207/5356

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