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    • 4. 发明公开
    • Hardware accelerator for performing division
    • Hardwarebeschleuniger zurDurchführungvon分部手续
    • EP1391812A1
    • 2004-02-25
    • EP02292060.7
    • 2002-08-20
    • Texas Instruments IncorporatedTEXAS INSTRUMENTS FRANCE
    • Giacalone, Jean-Pierre
    • G06F9/38G06F7/52
    • G06F7/535G06F9/3877G06F2207/5354
    • An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.
    • 一种用于允许数据处理系统中的数字信号处理器(DSP)执行高速分割操作的装置和方法。 在本发明的一个实施例中,在不超过两个周期内执行除法运算。 在本发明的另一个实施例中,分割操作是分数格式。 数据处理装置包括随机存取存储器,处理器(12,168)以及将所述随机存取存储器(104)耦合到所述处理器的接口(102),所述接口实现与所述处理器相关联的高速分割操作。 本发明的接口还可以与双处理器或协处理器系统组合以增加数据处理效率。