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1. 发明公开

EP1391812A1 Hardware accelerator for performing division 审中-公开
标题翻译： Hardwarebeschleuniger zurDurchführungvon分部手续
公开(公告)号：EP1391812A1
公开(公告)日：2004-02-25
申请号：EP02292060.7
申请日：2002-08-20
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Giacalone, Jean-Pierre
IPC分类号： G06F9/38 , G06F7/52
CPC分类号： G06F7/535 , G06F9/3877 , G06F2207/5354
摘要： An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.
摘要翻译：一种用于允许数据处理系统中的数字信号处理器（DSP）执行高速分割操作的装置和方法。在本发明的一个实施例中，在不超过两个周期内执行除法运算。在本发明的另一个实施例中，分割操作是分数格式。数据处理装置包括随机存取存储器，处理器（12,168）以及将所述随机存取存储器（104）耦合到所述处理器的接口（102），所述接口实现与所述处理器相关联的高速分割操作。本发明的接口还可以与双处理器或协处理器系统组合以增加数据处理效率。

2. 发明公开

EP0992885A1 Multiplier accumulator circuits 有权
标题翻译： Multiplizier-Akkumulatorschaltungen
公开(公告)号：EP0992885A1
公开(公告)日：2000-04-12
申请号：EP98402452.1
申请日：1998-10-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS FRANCE
发明人： Giacalone, Jean-Pierre , Theodorou, Francis , Boyadjian, Alain
IPC分类号： G06F7/544
CPC分类号： G06F7/5338 , G06F7/49921 , G06F7/49963 , G06F7/49968 , G06F7/5443 , G06F9/30014 , G06F9/3885 , G06F2207/382
摘要： A MAC unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.
摘要翻译：具有第一二进制操作数X，第二二进制操作数Y，第三二进制操作数，用于从所述第一和第二操作数产生多个部分乘积的布斯重写逻辑的MAC单元，用于减少部分乘积的华莱士树加法器，选择性地将减少的部分乘积与所述第三操作数组合，用于产生最终和的最终加法器和用于选择性舍入或饱和所述最终和的饱和电路。还提供了双MAC单元。

3. 发明授权

EP0992885B1 Multiplier accumulator circuits 有权
标题翻译：乘法累加器电路
公开(公告)号：EP0992885B1
公开(公告)日：2005-12-28
申请号：EP98402452.1
申请日：1998-10-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS FRANCE
发明人： Giacalone, Jean-Pierre , Theodorou, Francis , Boyadjian, Alain
IPC分类号： G06F7/544
CPC分类号： G06F7/5338 , G06F7/49921 , G06F7/49963 , G06F7/49968 , G06F7/5443 , G06F9/30014 , G06F9/3885 , G06F2207/382

4. 发明公开

EP0992882A3 Bit field processor 审中-公开
标题翻译： Bitfeldprozessor
公开(公告)号：EP0992882A3
公开(公告)日：2003-03-05
申请号：EP99400557.7
申请日：1999-03-08
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Laurenti, Gilbert , Giacalone, Jean-Pierre , Ego, Manuel, Le Mas des Micocouliers A1 , Couvrat, Marc
IPC分类号： G06F7/00 , G06F7/60
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30149
摘要： The processor can perform bit field expand and bit field extract functions under mask, as shown in figure 10. This functionality is particularly useful for the normalisation of floating-point numbers. The circuitry comprises encoders (1306-1312,1612-1618) and number-of-one-counters (1202-1236,1302) both partitioned in slices of 4 bits, and a two-level selector (1314-1322,1604-1608).

5. 发明公开

EP0899703A1 A navigational system 失效
标题翻译：导航系统
公开(公告)号：EP0899703A1
公开(公告)日：1999-03-03
申请号：EP97401986.1
申请日：1997-08-25
申请人： TEXAS INSTRUMENTS FRANCE , TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Hilbig, Hans-Martin , Giacalone, Jean-Pierre , Baumer, Jean-Claude
IPC分类号： G08G1/0968 , G01C21/20
CPC分类号： G08G1/096827 , G01C21/26 , G08G1/096844 , G08G1/096872
摘要： The navigational system, device and method of the present invention provide navigational information to the user derived from data signals received from a plurality of transmitters (20,22,24,26). The range to each of the plurality of transmitters (20,22,24,26) is then computed based upon the corresponding data signal received from the transmitters, and a current position relative to each of said plurality of transmitters is then determined. Geographical data relating to at least the current location of the user module 32 is stored in a memory 40, and selected geographical data relating to the current location of the user module 32 is retrieved from the memory 40 to provide an audio or video display 44. The computed route between the current position of the user module 32 and each of a plurality of way-points is then transmitted to a control processor which compares the determined route with routes received from other user modules and predicts traffic conditions for transmission back to the user module so that the route may be altered accordingly.
摘要翻译：本发明的导航系统，设备和方法为从用户接收的来自多个发射机（20,22,24,26）的数据信号提供导航信息给用户。然后基于从发射器接收的对应数据信号计算到多个发射器（20,22,24,26）中的每一个的距离，并且然后确定相对于所述多个发射器中的每一个的当前位置。至少涉及用户模块32的当前位置的地理数据被存储在存储器40中，并且从存储器40中检索与用户模块32的当前位置有关的选定地理数据以提供音频或视频显示器44。然后，将用户模块32的当前位置与多个路口点中的每一个之间的计算出的路线发送到控制处理器，该控制处理器将所确定的路线与从其他用户模块接收的路线进行比较，并且预测用于传输回用户的交通状况模块，以便可以相应地改变路线。

6. 发明授权

EP0992883B1 Rounding mechanism 有权
标题翻译：四舍五入机制
公开(公告)号：EP0992883B1
公开(公告)日：2004-05-19
申请号：EP98402458.8
申请日：1998-10-06
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Lombardot, Anne , Giacalone, Jean-Pierre , Theodorou, Francois
IPC分类号： G06F7/48 , G06F7/544
CPC分类号： G06F7/5443 , G06F7/48 , G06F7/49952 , G06F7/49963

7. 发明授权

EP0899703B1 A navigational system 失效
标题翻译：导航系统
公开(公告)号：EP0899703B1
公开(公告)日：2002-10-30
申请号：EP97401986.1
申请日：1997-08-25
申请人： TEXAS INSTRUMENTS FRANCE , TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Hilbig, Hans-Martin , Giacalone, Jean-Pierre , Baumer, Jean-Claude
IPC分类号： G08G1/0968 , G01C21/20
CPC分类号： G08G1/096827 , G01C21/26 , G08G1/096844 , G08G1/096872

8. 发明授权

EP0992884B1 Zero anticipation method and apparatus 有权
标题翻译：用于预见结果为零的方法和装置
公开(公告)号：EP0992884B1
公开(公告)日：2004-12-08
申请号：EP98402457.0
申请日：1998-10-06
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Lombardot, Anne , Giacalone, Jean-Pierre , Catan, Herve
IPC分类号： G06F7/50 , G06F7/02
CPC分类号： G06F7/508 , G06F7/02 , G06F7/49905 , G06F9/30094

9. 发明公开

EP0992895A1 Hardware accelerator for data processing systems 审中-公开
标题翻译： HardwarebeschleunigerfürDatenbearbeitungssystem
公开(公告)号：EP0992895A1
公开(公告)日：2000-04-12
申请号：EP98402463.8
申请日：1998-10-06
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Laurenti, Gilbert , Giacalone, Jean-Pierre , Djafarian, Karim , Laine, Armelle
IPC分类号： G06F9/38
CPC分类号： G06F9/3877
摘要： An apparatus and method for allowing a processor in a data processing system to perform multiple operations in a single cycle. In a preferred embodiment of the invention, the data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said data processing apparatus having the capability of processing multiple operations in a single cycle. In one embodiment of the invention, the interface is described as being a hardware accelerator (102). The invention provides the ability to perform multiple operations in a single cycle without the requirement of a dual or co-processor system in which a second processor works in parallel with a first processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.
摘要翻译：一种用于允许数据处理系统中的处理器在单个周期中执行多个操作的装置和方法。在本发明的优选实施例中，数据处理装置包括随机存取存储器，处理器（12,168）和将所述随机存取存储器（104）耦合到所述处理器的接口（102），所述数据处理装置具有在一个周期内处理多个操作的能力。在本发明的一个实施例中，该界面被描述为硬件加速器（102）。本发明提供了在单个周期中执行多个操作的能力，而不需要其中第二处理器与第一处理器并行工作的双处理器或协处理器系统。本发明的接口还可以与双处理器或协处理器系统组合以增加数据处理效率。

10. 发明公开

EP0992882A2 Bit field processor 审中-公开
标题翻译：位场处理器
公开(公告)号：EP0992882A2
公开(公告)日：2000-04-12
申请号：EP99400557.7
申请日：1999-03-08
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Laurenti, Gilbert , Giacalone, Jean-Pierre , Ego, Manuel, Le Mas des Micocouliers A1 , Couvrat, Marc
IPC分类号： G06F7/00
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30149
摘要： The processor can perform bit field expand and bit field extract functions under mask, as shown in figure 10. This functionality is particularly useful for the normalisation of floating-point numbers. The circuitry comprises encoders (1306-1312,1612-1618) and number-of-one-counters (1202-1236,1302) both partitioned in slices of 4 bits, and a two-level selector (1314-1322,1604-1608).
摘要翻译：处理器可以在掩码下执行位域扩展和位域提取功能，如图10所示。该功能对于浮点数的规范化特别有用。该电路包括分割成4位片段的编码器（1306-1312,1612-1618）和一个计数器（1202-1236,1302），以及两级选择器（1314-1322,1604-1608 ）。

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