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1. 发明公开

EP0576262A3 Apparatus for multiplying integers of many figures 失效
标题翻译：用于乘以许多数字的整数的装置
公开(公告)号：EP0576262A3
公开(公告)日：1994-03-23
申请号：EP93304879.5
申请日：1993-06-23
申请人： CANON KABUSHIKI KAISHA
发明人： Iwamura, Keiichi, c/o Canon Kabushiki Kaisha
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/533 , G06F7/722 , G06F7/723 , G06F2207/3852 , G06F2207/3892
摘要： A multiplier apparatus designed to multiply integers of many figures with a small circuit scale in such a manner that an input value is partitioned and multiplication is performed by taking account of carries. With respect to partitioned input values, partial multiplications are repeatedly performed in parallel with each other, and results of the partial multiplications are added by a plurality of adders. A carry occurring at each adder is added in the same adder or in an upper adder in the next cycle of addition. A circuit for this operation may be formed as a systolic array of identical processing elements to perform the operation in a pipe line processing manner.
摘要翻译：一种乘法器装置，设计用于以很小的电路规模乘以许多数字的整数，使得输入值被分割并且通过考虑载波来执行乘法。关于分割的输入值，部分乘法彼此并行地重复执行，并且部分乘法的结果由多个加法器相加。发生在每个加法器的进位在下一个加法周期中被加到同一加法器或上加法器中。用于该操作的电路可以形成为相同处理元件的脉动阵列以执行管线处理方式的操作。

2. 发明公开

EP0437107A3 Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing 失效
标题翻译：使用在线操作和位串行处理计算算术表达式的方法和装置
公开(公告)号：EP0437107A3
公开(公告)日：1992-10-14
申请号：EP90314370.9
申请日：1990-12-28
申请人： AIL SYSTEMS, INC.
发明人： Orsino, Francesco , Wang, Chung-Tao David
IPC分类号： G06F7/49 , G06F7/544
CPC分类号： G06F7/5443 , G06F7/4824 , G06F2207/3852
摘要： Method and apparatus for processing on-line operands A, B and C to produce the arithmetic expression S = (A × B) + C. In general, the apparatus comprises an input processing unit, an on-line multiplication unit, and an on-line serial addition unit. The input processing unit is for sequentially introducing the digits of operands A, B and C into the apparatus, where each digit is represented in a redundant binary number format. The multiplication means multiplies the sequence of digits of the operands A and B to produce the n-th product digit p n of the product P = A × B, with the most significant digit p 0 being computed first. The on-line addition unit adds the n-th product digit to the n-th digit of on-line operand C, so as to produce the n-th digit s n of the arithmetic expression S = (A × B) + C, with the most significant digit s 0 being produced first. In one embodiment, the input processing unit comprises a selective conversion subunit for selectively converting the digits of operands A, B and C sequentially entering the computational device, so that each digit is represented in a redundant number format. In such an embodiment, the redundant binary number format is characterized by signed digit numbers, and the selective conversion subunit comprises a binary-to-signed digit converter. Also, the input processing unit preferably includes a word-length control subunit for restraining the word length of the operands and intermediate words to a predetermined limit. In yet another embodiment, the apparatus hereof includes an arithmetic performance testing system for determining whether or not the arithmetic processor is functioning properly.

3. 发明公开

EP0419381A1 Circuit de détermination de valeur absolue pour des nombres exprimés en chiffres signés à base 2 失效
标题翻译： Grundzahl 2，AbsolutwertbestimmungsschaltungfürVorzeichenzifferzahlen mit Grundzahl 2。
公开(公告)号：EP0419381A1
公开(公告)日：1991-03-27
申请号：EP90420409.6
申请日：1990-09-18
申请人： FRANCE TELECOM
发明人： Privat, Gilles , Renaudin, Marc , Conq, Bernard
IPC分类号： G06F7/49
CPC分类号： G06F7/4824 , G06F2207/3852 , G06F2207/4812
摘要： La présente invention concerne un circuit de détermination de la valeur absolue d'un nombre, appliqué à des nombres exprimés selon une représentation en chiffres signés à base 2 dont chaque chiffre est codé par deux bits, le premier correspondant à une valeur positive et le deuxième à une valeur négative, ce circuit comprend des moyens (M1, M2, EOR) pour déterminer le signe du chiffre non nul de poids le plus élevé, des moyens (M3, M4) pour inverser ou non les bits de ce chiffre non nul de poids le plus élevé et les bits des chiffres suivants selon que ce chiffre non nul est négatif ou positif.
摘要翻译：本发明涉及一种用于数字的绝对值确定电路，该电路应用于根据其中每个数字由两位编码的基数-2有符号数字表示的数字，第一对应于正值，第二对应于该电路包括用于确定具有最大重要性的非零数字的符号的装置（M1，M2，EOR），用于反转或不重复该非零数字的最重要的位的装置（M3，M4）根据该非零数字是否为负数还是正数，以下数字的位。

4. 发明公开

EP2884403A1 APPARATUS AND METHOD FOR CALCULATING EXPONENTIATION OPERATIONS AND ROOT EXTRACTION 审中-公开
标题翻译： VORRICHTUNG UND VERFAHREN ZUR BERECHNUNG VON POTENZIERUNGEN UND RADIZIEREN
公开(公告)号：EP2884403A1
公开(公告)日：2015-06-17
申请号：EP13827706.6
申请日：2013-08-08
申请人： Universidade de Santiago de Compostela
发明人： DÍAZ BRUGUERA, Javier , VÁZQUEZ ÁLVAREZ, Álvaro
IPC分类号： G06F17/10
CPC分类号： G06F7/556 , G06F7/483 , G06F7/5525 , G06F2207/3852 , G06F2207/5356
摘要： An apparatus for general powering computation is disclosed. The apparatus is capable of computing a powering function of a floating-point number with an unrestricted exponent. The unrestricted exponent can be a fixed-point or a floating-point exponent. Additionally, the unrestricted exponent can be an inverse of a number in order to enable for q-th root computation using the same hardware processor and architecture.
摘要翻译：公开了一种用于一般供电计算的装置。该装置能够计算具有无限制指数的浮点数的功率函数。不受限制的指数可以是定点或浮点指数。另外，无限制指数可以是数字的倒数，以便能够使用相同的硬件处理器和体系结构进行第q个根计算。

5. 发明授权

EP2189897B1 Multiplikation einer ganzen Zahl mit einer Gleitkommazahl 有权
标题翻译：的整数的乘法与浮点数
公开(公告)号：EP2189897B1
公开(公告)日：2013-04-24
申请号：EP08020118.9
申请日：2008-11-19
申请人： VEGA Grieshaber KG
发明人： Kopp, Manfred
IPC分类号： G06F7/487 , G06F7/527 , G06F7/499 , H03M7/24
CPC分类号： G06F7/4876 , G06F7/49963 , G06F7/5272 , G06F2207/3852 , H03M7/24

6. 发明授权

EP0437107B1 Method and apparatus for computing arithmetic expressions using on-line operands and bit-serial processing 失效
标题翻译：对于使用在线操作数和位串行处理计算的算术表达式的方法和装置
公开(公告)号：EP0437107B1
公开(公告)日：1998-08-26
申请号：EP90314370.9
申请日：1990-12-28
申请人： AIL SYSTEMS, INC.
发明人： Orsino, Francesco , Wang, Chung-Tao David
IPC分类号： G06F7/49 , G06F7/544
CPC分类号： G06F7/5443 , G06F7/4824 , G06F2207/3852

7. 发明公开

EP0398568A3 Multiplier circuit 失效
标题翻译：多路复用电路
公开(公告)号：EP0398568A3
公开(公告)日：1992-08-05
申请号：EP90304898.1
申请日：1990-05-04
申请人： AT&T Corp.
发明人： Rao, Sailesh Krishna
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/49994 , G06F2207/3852
摘要： In a multiplier for binary numbers represented in two's complement notation, the need to perform sign-bit extension in order to combine the partial products is avoided by representing the value represented by the sign bits of all the partial products as a two's complement number in its own right. The bits of that number, rather than the original sign bits, are then used in the partial product addition. Since (as with all two's complement numbers) all the bits of the sign-bit-value word are guaranteed to have positive significance (except for the left-most one), the digits of the partial products can then be directly added without the need for sign bit extension.

8. 发明公开

EP0493835A2 An arithmetic operation unit having bit inversion function 失效
标题翻译：算术操作可以进行位转换。
公开(公告)号：EP0493835A2
公开(公告)日：1992-07-08
申请号：EP91122381.6
申请日：1991-12-30
申请人： NEC CORPORATION
发明人： Yoshida, Makoto, c/o NEC Corporation
IPC分类号： G06F7/48 , G06F7/50
CPC分类号： G06F7/503 , G06F7/575 , G06F2207/3852
摘要： A bit-inversion arithmetic operation unit comprises a first carry signal line for propagating a carry signal from a more significant bit position side to a less significant bit position side, and a second carry signal line for propagating a carry signal from a less significant bit position side to a more significant bit position side. A common logic circuit performs at least a portion of a carry control including a carry propagation of the first and second carry signals and a carry generation. A switching and logic circuit responds to a required arithmetic operation mode so as tp control the common logic circuit and to perform the remaining portion of the carry control including the carry propagation of the first and second carry signals and the carry generation.
摘要翻译：位反转算术运算单元包括用于将进位信号从更高有效位位置侧传播到较低有效位位置侧的第一进位信号线和用于从较低有效位位置传播进位信号的第二进位信号线侧到更重要的位位置。公共逻辑电路执行包括第一和第二进位信号的进位传播和进位产生的进位控制的至少一部分。开关和逻辑电路响应于所需的算术运算模式，以便tp控制公共逻辑电路，并执行进位控制的剩余部分，包括第一和第二进位信号和进位产生的进位传播。

9. 发明授权

EP2037622B1 Method for receiving serial transmission signal 有权
标题翻译：一种用于接收传输的串行信号的方法
公开(公告)号：EP2037622B1
公开(公告)日：2013-03-20
申请号：EP08164361.1
申请日：2008-09-15
申请人： HTC Corporation
发明人： Huang, David , Lee, Chi-Feng , Chou, Hsiu-Hung
IPC分类号： H04L9/18 , G06F7/504
CPC分类号： G06F7/5045 , G06F2207/3852 , H04L9/06

10. 发明公开

EP1423785A2 POWER RAISING CIRCUIT 审中-公开
标题翻译：幂
公开(公告)号：EP1423785A2
公开(公告)日：2004-06-02
申请号：EP02775203.9
申请日：2002-08-14
申请人： Telecom Italia S.p.A.
发明人： ETTORRE, Donato,c/o Telecom Italia S.p.a. , MELIS, Bruno,c/o Telecom Italia S.p.a. , RUSCITTO, Alfredo,c/o Telecom Italia S.p.a.
IPC分类号： G06F7/552
CPC分类号： G06F7/552 , G06F2207/3852 , G06F2207/5523
摘要： An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Zn) into a first part (msb(Zn)) that is the power of 2 immediately lower than or equal to the input signal and a second part (Zn - msb(Zn)) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.

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