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1. 发明公开

EP4455896A1 DATA REFRESH CYCLE FOR ASYNCHRONOUS DEVICE COMMUNICATION 审中-公开
公开(公告)号：EP4455896A1
公开(公告)日：2024-10-30
申请号：EP24173068.8
申请日：2024-04-29
申请人： Hamilton Sundstrand Corporation
发明人： ESWARAN, Pravinsharma Kaliyannan , NALLATHAMBI, Annamalai , MOON, Sneha Ashok , BHOSLE, Akansha
IPC分类号： G06F13/16 , G06F13/362 , G06F13/40 , G06F13/42 , H04L12/40 , G06F13/12 , G06F5/06 , H04L49/90 , G06F15/167
CPC分类号： G06F13/1689 , G06F13/3625 , G06F13/4059 , G06F13/4063 , G06F13/4269 , G06F13/4226 , G06F13/4213 , H04L12/40032 , H04L12/4015 , G06F13/124 , H04L49/9094 , G06F15/167
摘要： An asynchronous communication system configured to operate a MIL-1553 protocol. The system includes: a bus (102); a bus controller (104) coupled to the bus (102) that is configured to control access to the bus (102); a remote terminal (106) connected to the bus (102); a device controller (108) connected to the remote terminal (106); and a read/write overlap avoidance latch (280) connected to the remote terminal (106). The read/write overlap avoidance latch (280) provides an active signal (270, 282) to the device controller (108) that prevents the device controller (108) from writing data to the remote terminal (106) while the bus controller (104) is reading data from the device controller (108) during a read cycle.

2. 发明公开

EP2856690A4 UNIVERSAL SYNCHRONIZATION ENGINE BASED ON PROBABILISTIC METHODS FOR GUARANTEE OF LOCK IN MULTIFORMAT AUDIO SYSTEMS 有权转让
标题翻译：基于阻断担保的概率方法更SIZED音响系统通用机械SYNC
公开(公告)号：EP2856690A4
公开(公告)日：2016-02-17
申请号：EP13796542
申请日：2013-03-14
申请人： BLACKBERRY LTD
发明人： POULSEN JENS KRISTIAN
IPC分类号： H04L7/00 , G06F13/38 , H04L1/24 , H04L12/40
CPC分类号： G06F13/3625 , G06F1/12 , H04J3/06 , H04L1/1607 , H04L7/041 , H04L7/042 , H04L7/048 , H04L7/10 , H04L2001/0094

3. 发明公开

EP2757484A1 Apparatus and method for dynamically aligned source synchronous receiver 有权
标题翻译：动力学和动力学
公开(公告)号：EP2757484A1
公开(公告)日：2014-07-23
申请号：EP13159437.6
申请日：2013-03-15
申请人： VIA Technologies, Inc.
发明人： Canac, Vanessa S. , Lundberg, James R.
IPC分类号： G06F13/42
CPC分类号： G11C7/1072 , G06F1/12 , G06F13/3625 , G06F13/4068 , G06F13/4217 , G06F13/4243 , G11C8/18
摘要： An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals.
摘要翻译：一种包括同步延迟接收器的装置，其接收多个径向分布的选通信号中的一个和数据位，并且延迟数据位的记录传播时间。同步延迟接收器具有第一多个匹配的反相器，第一复用器和位接收器。第一组多个匹配的逆变器产生数据位的连续延迟版本。第一个多路复用器在一个指示传播时间的延迟总线上接收一个值，并选择与该值对应的数据位的连续延迟版本中的一个。位接收器接收数据位的连续延迟版本中的一个和多个径向分布的选通信号中的一个，并且在断言多个数据位之后注册数据位的连续延迟版本中的一个的状态的分布式选通信号。

4. 发明公开

EP2686774A1 MEMORY INTERFACE 有权
标题翻译：存储器接口
公开(公告)号：EP2686774A1
公开(公告)日：2014-01-22
申请号：EP11860733.2
申请日：2011-03-14
申请人： Hewlett-Packard Development Company, L.P.
发明人： UDIPI, Aniruddha Nagendran , MURALIMANOHAR, Naveen , JOUPPI, Norman Paul , BALASUBRAMONIAN, Rajeev , DAVIS, Alan Lynn
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/3625 , G06F13/1605 , G06F13/1689
摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based, at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing a read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

5. 发明公开

EP2539823A4 TIME MULTIPLEXING AT DIFFERENT RATES TO ACCESS DIFFERENT MEMORY TYPES 有权转让
标题翻译：用于访问不同存储器类型的不同速率的多工艺处理
公开(公告)号：EP2539823A4
公开(公告)日：2013-07-31
申请号：EP10846793
申请日：2010-11-23
申请人： RAMBUS INC
发明人： SHAEFFER IAN
IPC分类号： G06F13/16
CPC分类号： G06F13/1694 , G06F13/287 , G06F13/3625 , G06F13/4221 , G06F13/4234
摘要： A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

6. 发明公开

EP2453361A1 Apparatus and method for arbitrating bus 审中-公开
标题翻译： Vorrichtung und Verfahren zur Busvermittlung
公开(公告)号：EP2453361A1
公开(公告)日：2012-05-16
申请号：EP11188771.7
申请日：2011-11-11
申请人： Samsung Electronics Co., Ltd , SNU R&DB Foundation
发明人： Lee, Hyuk Jae , Kwon, Kwon Taek , Jung, Seok Yoon , Kim, Kyu Dong , Woo, Deum Ji
IPC分类号： G06F13/362
CPC分类号： G06F13/3625
摘要： A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters.
摘要翻译：提供一种总线仲裁装置和方法。可以基于主特性将多个主机分类为主机类型，并且可以执行总线仲裁。因此，可以防止总线分配到预定的主机，并且可以通过解决多个主机之间的性能不均衡分配的问题来改善总线系统的总体性能。

7. 发明公开

EP2343656A1 Network scheduling method, computer program product and network-on-chip 审中-公开
标题翻译： Netzwerkkoordinationsverfahren，Computerprogrammprodukt und Netzwerk-on-Chip
公开(公告)号：EP2343656A1
公开(公告)日：2011-07-13
申请号：EP09179321.6
申请日：2009-12-15
申请人： NXP B.V.
发明人： Pontius, Tim
IPC分类号： G06F13/362
CPC分类号： G06F13/3625
摘要： Disclosed is a method (200) of scheduling communications over a network (300) comprising a plurality of connections to a shared resource (340), comprising: defining a communication schedule (100) comprising a total number of time slots (110) for granting a connection periodical access to the shared resource; and, for each connection: assigning a first available time slot (110) in the communication schedule; and assigning a second available time slot (110) in the communication schedule having a minimal delay with respect to the first time slot (110), said minimal delay being at least the expected combined latency of the network (300) and the shared resource (340) for responding to a request for said shared resource by the connection. A computer program product and network-on-chip (300) are also disclosed.
摘要翻译：公开了一种通过网络（300）调度通信的方法（200），包括到共享资源（340）的多个连接，包括：定义通信调度（100），其包括总数量的时隙（110）连接对共享资源的定期访问; 并且对于每个连接：在通信调度中分配第一可用时隙（110）; 以及在所述通信调度中分配相对于所述第一时隙（110）具有最小延迟的第二可用时隙（110），所述最小延迟至少为所述网络（300）和所述共享资源（300）的预期组合等待时间 340），用于通过所述连接响应对所述共享资源的请求。还公开了一种计算机程序产品和片上网络（300）。

8. 发明公开

EP1187032A1 Time-out counter for multiple transaction bus system bus bridge 有权
标题翻译： ZeitablaufzählerfürMehrtransaktionsbussystem-Busbrücke
公开(公告)号：EP1187032A1
公开(公告)日：2002-03-13
申请号：EP01000442.2
申请日：2001-09-10
申请人： Texas Instruments Inc.
发明人： Jahnke, Steven R. , Hamakawa, Hiromichi
IPC分类号： G06F13/40
CPC分类号： G06F13/24 , G06F13/3625 , G06F13/4031
摘要： The time-out counter (302) of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt (364) if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter (302) is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus.
摘要翻译：本发明的超时计数器（302）在总线桥中为第一总线主机提供一种能力，用于产生超时中断（364），如果在一段时间内没有给予第二总线的控制，则在第二班车仲裁时间过长。超时计数器（302）可编程高达16位，允许软件选择超时长度。如果所使用的仲裁方式否则允许第二总线主机对第一总线进行绝对控制，则该超时功能是有用的。

9. 发明公开

EP1143342A2 Method and apparatus for processing input/output request using a plurality of channel buses 失效
标题翻译： Vefahren并且在多个信道总线的I / O请求处理装置
公开(公告)号：EP1143342A2
公开(公告)日：2001-10-10
申请号：EP01115734.4
申请日：1995-07-31
申请人： FUJITSU LIMITED
发明人： Koyama, Susumu
IPC分类号： G06F13/12
CPC分类号： G06F13/24 , G06F3/0601 , G06F13/126 , G06F13/3625 , G06F2003/0698
摘要： An apparatus for processing an input/output request from an upper unit 14-i using a plurality of channel buses 18-i of different transfer speeds comprises: a plurality of input/output ports 20-i connected to a plurality of channel units on the upper unit side through the plurality of channel buses; and a command analysis executing section 92, 94 provided for each input/output port for analyzing whether a command received in association with an activation request during the coupling of another input/output port is a command that can be executed or not, and when it is an executable command accepting the activation request and executing a command process for internal resources.
摘要翻译：用于输入/输出请求的处理从在上部单元14-i中使用信道总线的多个不同的转移的18-i的速度包括一种设备：输入/输出端口的多个检测器20-i的连接到信道单元上的一个多元通过信道总线的多个上部单元侧; 并执行为每个输入/输出端口，用于分析另一输入/输出端口的耦合过程中无论是在相关联地接收与激活请求的命令部92，94的命令分析是一个命令并可以执行与否，并且当它是可执行命令接受激活请求，并且执行一个命令过程为内部资源。

10. 发明公开

EP0703535A3 Method and apparatus for processing input/output requests from a plurality of channel buses 失效
标题翻译：用于从多个信道总线的处理输入/输出请求的方法和装置
公开(公告)号：EP0703535A3
公开(公告)日：1996-10-02
申请号：EP95305348.5
申请日：1995-07-31
申请人： FUJITSU LIMITED
发明人： Koyama, Susumu, c/o Fujitsu Limited
IPC分类号： G06F13/362
CPC分类号： G06F13/24 , G06F3/0601 , G06F13/126 , G06F13/3625 , G06F2003/0698
摘要： In order to share out central resources fairly between low-speed and high-speed input/output ports 20-1, 20-2 of an input/output control unit, an activation time between a time point when an end status associated with the end of a transfer is sent and a time point when an activation request is received is measured and stored in a memory 48. When the high-speed port receives an activation request from a high-speed channel, the activation time in the memory measured with respect to the low-speed port is read out and during this activation time an input/output request for the low-speed port is preferentially accepted. To provide the activation time for the low-speed port the minimum time, average time and maximum time are obtained from the result of the measurement. Any of these three times can be selected as the activation time in order substantially to equalize the busy ratios of the high-speed and low-speed ports. Allocation can also be made in alternative ways, for instance by reference to the number of requests which meet with a busy signal.

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