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1. 发明公开

EP2353058A4 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
标题翻译：低功耗模式TAKTGESTEUERTEM MESOCHRONES信令系统
公开(公告)号：EP2353058A4
公开(公告)日：2014-04-09
申请号：EP09837752
申请日：2009-07-09
申请人： RAMBUS INC
发明人： WARE FREDERICK A , PALMER ROBERT E , POULTON JOHN W , FULLER ANDREW M
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02B60/1228 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

2. 发明公开

EP1990729A4 PROCESSOR DEVICE AND INSTRUCTION PROCESSING METHOD 审中-公开
标题翻译：处理器设备和订单处理
公开(公告)号：EP1990729A4
公开(公告)日：2010-08-25
申请号：EP06714758
申请日：2006-02-27
申请人： FUJITSU LTD
发明人： UKAI MASAKI
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0857 , G06F12/0859

3. 发明公开

EP1990730A1 CACHE CONTROLLER AND CACHE CONTROL METHOD 有权
标题翻译： CACHE-STEUERUNG UND CACHE-STEUERVERFAHREN
公开(公告)号：EP1990730A1
公开(公告)日：2008-11-12
申请号：EP06714759.5
申请日：2006-02-27
申请人： Fujitsu Ltd.
发明人： UKAI, Masaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0844 , G06F12/0857 , G06F12/0859 , G06F2212/1016 , G06F2212/1056
摘要： To retrieve large amounts of data to be written to a cache memory, achieving downsizing and cost reduction of a chip. An external bus controller (101) inputs MI data supplied from any of external buses to an MI data RAM (102) in synchronization with the control performed by an input and output controller (105). The MI data RAM (102) stores therein the MI data, and if a data register (108) has an space available for retrieving MI data, the MI data RAM (102) outputs the MI data to the data register (108) via a selector (104). The input and output controller (105) inputs the MI data flowing in the external bus controller (101) to the MI data RAM (102) in a CPU cycle. The data register (108) once retrieves MI data to be written to an L2 cache (111), and then writes the MI data to the L2 cache (111).
摘要翻译：为了检索要写入高速缓冲存储器的大量数据，实现芯片的小型化和降低成本。与由输入和输出控制器（105）执行的控制同步，外部总线控制器（101）将从任何外部总线提供的MI数据输入到MI数据RAM（102）。 MI数据RAM（102）在其中存储MI数据，并且如果数据寄存器（108）具有可用于检索MI数据的空间，MI数据RAM（102）经由以下操作将MI数据输出到数据寄存器（108）：选择器（104）。输入和输出控制器（105）以CPU周期将在外部总线控制器（101）中流动的MI数据输入到MI数据RAM（102）。数据寄存器（108）一次检索要写入L2高速缓存（111）的MI数据，然后将MI数据写入L2高速缓存（111）。

4. 发明公开

EP0398523A2 A device for data i/o and execution support in digital processors 失效
标题翻译： Dateningabe - / - ausgabevorrichtung undAusführungsunterstützung在digitalen Prozessoren。
公开(公告)号：EP0398523A2
公开(公告)日：1990-11-22
申请号：EP90304460.0
申请日：1990-04-25
申请人： HITACHI, LTD.
发明人： Patel, Chandravadan N. , Blasco, Richard WM. , Chan, Kenneth M. , Chen, Shieh C.
IPC分类号： G06F13/12 , G06F12/08
CPC分类号： G06F12/0853 , G06F12/0857
摘要： A device for simultaneous data input and output and execution support in digital processors including a plurality of controllable input and output ports (6,8,12) for inputting and outputting data from the device, a data cache memory (10) which is selectively connectable to each of the plurality of input and output ports (6,8,12) and a controller (20) for controlling the plurality of input and output ports (6,8,12) and the data cache memory (10) for effecting a transfer of data between any of the plurality of input and output ports (6,8,12) or the data cache memory (10).
摘要翻译：一种用于在数字处理器中同时进行数据输入和输出和执行支持的装置，包括用于从设备输入和输出数据的多个可控输入和输出端口（6,8,12），可选择地连接的数据高速缓存存储器到多个输入和输出端口（6,8,12）中的每一个以及用于控制多个输入和输出端口（6,8,12）和数据高速缓冲存储器（10）的控制器（20），用于实现在多个输入和输出端口（6,8,12）或数据高速缓冲存储器（10）中的任何一个之间传送数据。

5. 发明授权

EP2370975B1 CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM 有权转让
标题翻译：与时钟传送低功率通知系统
公开(公告)号：EP2370975B1
公开(公告)日：2016-09-28
申请号：EP09837751.8
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
IPC分类号： G11C7/22 , G11C11/4076 , G11C7/10 , G11C11/4096 , G11C7/04 , G06F13/16 , G06F12/08 , G06F13/36 , G06F1/12 , G06F1/32 , G06F9/38
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

6. 发明授权

EP2159704B1 CACHE MEMORY CONTROL DEVICE AND PIPELINE CONTROL METHOD 有权
标题翻译： CACHE存储器控制装置和管道的控制方法
公开(公告)号：EP2159704B1
公开(公告)日：2013-06-26
申请号：EP07790186.6
申请日：2007-06-20
申请人： Fujitsu Limited
发明人： SHIMIZUNO, Koken , ISHIMURA, Naoya
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857

7. 发明公开

EP2356657A1 MESOCHRONOUS SIGNALING SYSTEM WITH MULTIPLE POWER MODES 审中-公开
标题翻译：具有多个电源模式MESOCHRONES信令系统
公开(公告)号：EP2356657A1
公开(公告)日：2011-08-17
申请号：EP09837755.9
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A. , POULTON, John, W. , PALMER, Robert, E.
IPC分类号： G11C11/407 , G11C8/00 , H03L7/081
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

8. 发明授权

EP1221095B1 AN ARBITRATION PROTOCOL FOR A SHARED DATA CACHE 有权
标题翻译：为了一个共同的DATA BUFFER仲裁
公开(公告)号：EP1221095B1
公开(公告)日：2004-04-07
申请号：EP00965520.0
申请日：2000-09-29
申请人： Sun Microsystems Inc.
发明人： TREMBLAY, Marc , KOWALCZYK, Andre , TIRUMALA, Anup, S.
IPC分类号： G06F9/52 , G06F9/46 , G06F12/08
CPC分类号： G06F9/5016 , G06F12/0857 , G06F12/0859 , G06F13/1605
摘要： A method and computer system for resolving simultaneous requests from multiple processing units to load from or store to the same shared resource. When the colliding requests come from two different processing units, the first processing unit is allowed access to the structure in a predetermined number of sequential collisions and the second device is allowed access to the structure in a following number of sequential collisions. The shared resource can be a fill buffer, where a collision involves attempts to simultaneously store in the fill buffer. The shared resource can be a shared write back buffer, where a collision involves attempts to simultaneously store in the shared write back buffer. The shared resource can be a data cache unit, where a collision involves attempts to simultaneously load from a same data space in the data cache unit. A collision can also involve an attempt to load and store from a same resource and in such case the device that attempts to load is favored over the device that attempts to store.

9. 发明公开

EP1221095A1 AN ARBITRATION PROTOCOL FOR A SHARED DATA CACHE 有权
标题翻译：为了一个共同的DATA BUFFER仲裁
公开(公告)号：EP1221095A1
公开(公告)日：2002-07-10
申请号：EP00965520.0
申请日：2000-09-29
申请人： Sun Microsystems Inc.
发明人： TREMBLAY, Marc , KOWALCZYK, Andre , TIRUMALA, Anup, S.
IPC分类号： G06F9/52
CPC分类号： G06F9/5016 , G06F12/0857 , G06F12/0859 , G06F13/1605
摘要： A method and computer system for resolving simultaneous requests from multiple processing units to load from or store to the same shared resource. When the colliding requests come from two different processing units, the first processing unit is allowed access to the structure in a predetermined number of sequential collisions and the second device is allowed access to the structure in a following number of sequential collisions. The shared resource can be a fill buffer, where a collision involves attempts to simultaneously store in the fill buffer. The shared resource can be a shared write back buffer, where a collision involves attempts to simultaneously store in the shared write back buffer. The shared resource can be a data cache unit, where a collision involves attempts to simultaneously load from a same data space in the data cache unit. A collision can also involve an attempt to load and store from a same resource and in such case the device that attempts to load is favored over the device that attempts to store.

10. 发明公开

EP4425342A1 METHOD FOR STORING AND READING CACHED DATA AND DEVICE 审中-实审
公开(公告)号：EP4425342A1
公开(公告)日：2024-09-04
申请号：EP24160176.4
申请日：2024-02-28
申请人： YUSUR Technology Co., Ltd.
发明人： JIN, Jian , ZHANG, Shuanglin
IPC分类号： G06F12/0842 , G06F12/0844 , G06F12/0846 , G06F12/0855 , G06F12/0886 , G06F12/084
CPC分类号： Y02D10/00 , G06F12/0857 , G06F12/0842 , G06F12/0886 , G06F12/0851 , G06F12/0844 , G06F2212/102420130101 , G06F12/084
摘要： Embodiments of the present disclosure provide a method for storing and reading cached data and a device. The method for storing and reading cached data includes: in response to receiving to-be-cached data, segmenting the to-be-cached data sequentially into at least two pieces of first fragmented data; writing the first fragmented data sequentially into first storage particles of at least two storage blocks in a time division multiplexing manner, and ensuring that the first fragmented data written into the respective first storage particles are different from each other; and saving a correspondence between first identifiers of the to-be-cached data and addresses of the first storage particles to a resource management table. The fragmented data are stored and read in the time division multiplexing manner, and the fragmented data corresponding to a complete data are stored in different storage blocks, so a plurality of data can be stored and read in a complete data storage and read process, thereby reducing read and write time overhead during the execution of a large number of buffered data storage and read tasks.

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