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1. 发明公开

EP4443497A1 SEMICONDUCTOR PACKAGE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND LEAD FRAME 审中-公开
公开(公告)号：EP4443497A1
公开(公告)日：2024-10-09
申请号：EP24162733.0
申请日：2024-03-11
申请人： NXP USA, Inc.
发明人： Song, Jian , Li, Jun
IPC分类号： H01L23/495 , H01L21/48
CPC分类号： H01L23/49541 , H01L23/49548 , H01L21/4842
摘要： A semiconductor package has top and bottom surfaces and includes a vertical direction extending from the top surface to the bottom surface. The semiconductor package comprises a semiconductor die and a lead frame. At least one of each pair of neighboring leads comprises an elongate lug extending towards the other of the pair of neighboring leads. A region of each lug remote from the lead has a thickness which is smaller than a full thickness of the lead frame. The semiconductor package further comprising molding compound encapsulating the semiconductor die and forming the semiconductor package. The molding compound fills the spaces between the leads and fills spaces separating the die pad from the leads.

2. 发明授权

EP4002695B1 HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES WITH HOT CARRIER INJECTION DAMAGE PROTECTION 有权
公开(公告)号：EP4002695B1
公开(公告)日：2024-10-09
申请号：EP21205268.2
申请日：2021-10-28
IPC分类号： H03K17/16
CPC分类号： H03K19/00315 , H03K19/018521 , H03K17/102 , H03K17/693 , H03K17/162

3. 发明公开

EP4435786A1 MEMORY WITH ONE-TIME PROGRAMMABLE (OTP) CELLS 审中-公开
公开(公告)号：EP4435786A1
公开(公告)日：2024-09-25
申请号：EP24164499.6
申请日：2024-03-19
申请人： NXP USA, Inc.
发明人： Roy, Anirban , Mahatme, Nihaar N. , Choy, Jon Scott
IPC分类号： G11C11/16 , G11C17/16 , G11C17/18 , G11C7/10 , G11C7/16
CPC分类号： G11C11/1675 , G11C17/18 , G11C7/1078 , G11C11/161 , G11C11/1677 , G11C11/1697 , G11C7/16 , G11C17/16
摘要： A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

4. 发明公开

EP4429173A1 PERSONAL AREA NETWORK SECURITY 审中-公开
公开(公告)号：EP4429173A1
公开(公告)日：2024-09-11
申请号：EP23205595.4
申请日：2023-10-24
申请人： NXP USA, Inc.
发明人： Caciuloiu, Cristian
IPC分类号： H04L9/40
CPC分类号： H04L63/0464 , H04L63/0428 , H04L63/062 , H04L63/0281
摘要： The disclosure relates to a method and a router for securely connecting a device to a wireless personal area network. Example embodiments include a method (300) of connecting a joiner device (212) to a wireless personal area network (PAN), the PAN comprising a plurality of devices configured to communicate messages encrypted with a first network key across the PAN, the plurality of devices comprising a router (311), the method comprising: i) receiving by the router (311) from the joiner device (212) a join request message encrypted by a second network key; ii) sending by the router (311) to the joiner device (212) a join confirmation message that contains a third network key; iii) receiving subsequent incoming messages (314) by the router (311) from the joiner device (212) encrypted by the third network key, re-encrypting by the router (311) each subsequent incoming message with the first network key and transmitting the re-encrypted subsequent incoming messages (315) to other devices in the PAN (100, 600); and iv) receiving by the router (311) from other devices in the PAN (100, 600) subsequent outgoing messages (316) for the joiner device (212) encrypted by the first network key, re-encrypting the subsequent outgoing messages with the third network key and sending the re-encrypted subsequent outgoing messages (317) by the router (311) to the joiner device (212).

5. 发明授权

EP3462500B1 BIDIRECTIONAL POWER MOSFET STRUCTURE 有权
公开(公告)号：EP3462500B1
公开(公告)日：2024-09-11
申请号：EP18167136.3
申请日：2018-04-12
IPC分类号： H01L29/78 , H01L21/336 , H01L29/08
CPC分类号： H01L29/66734 , H01L29/7813 , H01L29/086 , H01L29/7803

6. 发明公开

EP4414850A1 SYSTEMS AND METHODS FOR DEBUGGING MULTI-CORE PROCESSORS WITH CONFIGURABLE ISOLATED PARTITIONS 审中-公开
公开(公告)号：EP4414850A1
公开(公告)日：2024-08-14
申请号：EP24156846.8
申请日：2024-02-09
申请人： NXP USA, Inc.
发明人： Miller, Gary L. , Singh, Devendra Bahadur , Gamoneda, Jonathan , Kimelman, Paul , Yishay, Oded
IPC分类号： G06F11/36 , G01R31/317 , G06F11/22
CPC分类号： G06F11/3656 , G06F11/2242 , G01R31/31705 , G06F11/362
摘要： Systems and methods for debugging multi-core processors with configurable isolated partitions have been described. In an illustrative, non-limiting embodiment, an integrated circuit, may include: a plurality of Cross-Trigger Matrices (CTMs) configured to establish a debug network among a plurality of muti-cluster tiles (MCTs), where each MCT includes a plurality of processor cores, and where each processor core is assigned to a respective isolated partition of processor cores; and a System Interface (SI) coupled to the plurality of CTMs, where the SI is configured to control the plurality of CTMs to enable or disable at least a portion of the debug network to allow an isolated partition to be debugged independently of another isolated partition. A method may include enabling or disabling, by the SI, buses between the MCTs to create isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.

7. 发明授权

EP3929622B1 RADAR SYSTEM 有权
公开(公告)号：EP3929622B1
公开(公告)日：2024-08-07
申请号：EP20182372.1
申请日：2020-06-25
IPC分类号： G01S13/58 , G01S13/34 , G01S13/42 , G01S13/87
CPC分类号： G01S13/583 , G01S13/34 , G01S13/42 , G01S13/878

8. 发明授权

EP4075674B1 ANTENNA TUNER FOR A BEAMFORMING ANTENNA ARRAY 有权
公开(公告)号：EP4075674B1
公开(公告)日：2024-07-03
申请号：EP22166442.8
申请日：2022-04-04
IPC分类号： H04B1/04 , H04B1/18 , H04B7/06 , H04B7/08 , H03H7/40
CPC分类号： H04B1/0458 , H04B1/18 , H03H7/40 , H04B7/0695 , H04B7/088

9. 发明公开

EP4383044A1 ARCHITECTURE FOR MANAGING ASYNCHRONOUS RESETS IN A SYSTEM-ON-A-CHIP 审中-公开
公开(公告)号：EP4383044A1
公开(公告)日：2024-06-12
申请号：EP23211465.2
申请日：2023-11-22
申请人： NXP USA, Inc.
发明人： Abhishek, Kumar , Srivastava, Neha , Zheng, Yi , Kumar, Nishant
IPC分类号： G06F1/24 , H03K17/22
CPC分类号： G06F1/24 , H03K17/22
摘要： Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

10. 发明公开

EP4380060A1 RDAC LADDER WITH ADAPTIVE BIASING TO REDUCE THE REFERENCE VARIATION ACROSS TEMPERATURE 审中-公开
公开(公告)号：EP4380060A1
公开(公告)日：2024-06-05
申请号：EP23211103.9
申请日：2023-11-21
申请人： NXP USA, Inc.
发明人： Goyal, Saurabh , Thakur, Krishna , Tripathi, Divya , Jain, Deependra Kumar
IPC分类号： H03M1/76 , H03M1/08 , H03M1/68 , H03K17/14 , H03K17/693
CPC分类号： H03M1/765 , H03M1/68 , H03M1/089 , H03K17/145 , H03K17/693
摘要： A low current, adaptively-biased switched resistor digital-to-analog converter (RDAC) circuit, method and apparatus are provided with a coarse trim ladder and a fine trim ladder connected with a plurality of NFET switches to generate an output reference voltage from an input supply voltage, where the bulk semiconductor substrate regions for the NFET switches in at least the fine trim ladder are driven by a unity gain buffer which is connected in feedback to receive the output reference voltage and to generate a buffered reference voltage which is directly connected to bulk semiconductor regions of the NFET switches, thereby providing a low current, low circuit area solution with reduced leakage current and temperature variation.

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