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1. 发明公开

EP4362022A1 COLUMN REPAIR IN A MEMORY SYSTEM USING A REPAIR CACHE 审中-公开
公开(公告)号：EP4362022A1
公开(公告)日：2024-05-01
申请号：EP23203321.7
申请日：2023-10-12
申请人： NXP USA, Inc.
发明人： Choy, Jon Scott , Strauss, Timothy , Storms, Maurits Mario Nicolaas , Hume, Christopher Nelson , Wagemans, Silvia
IPC分类号： G11C29/00 , G11C7/10 , G11C11/16 , G11C29/44
CPC分类号： G11C29/789 , G11C29/76 , G11C29/816 , G11C29/846 , G11C29/4401 , G11C2029/440220130101 , G11C29/808 , G11C29/80 , G11C11/1655 , G11C7/1066 , G11C7/1069
摘要： A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

2. 发明公开

EP4310845A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) WITH END OF LIFE MARGIN SENSOR 审中-实审
公开(公告)号：EP4310845A1
公开(公告)日：2024-01-24
申请号：EP23177547.9
申请日：2023-06-06
申请人： NXP USA, Inc.
发明人： Roy, Anirban , Harp, Thomas Stephen , Mahatme, Nihaar N. , Choy, Jon Scott
IPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.

3. 发明授权

EP3249655B1 NONVOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) SYSTEM HAVING A STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY AND A RESISTIVE MEMORY ARRAY 有权
公开(公告)号：EP3249655B1
公开(公告)日：2019-07-10
申请号：EP17172930.4
申请日：2017-05-25
申请人： NXP USA, Inc.
发明人： Roy, Anirban , Sadd, Michael A. , Choy, Jon Scott
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00 , G11C11/419 , G11C27/02 , H01L27/11

4. 发明授权

EP3200191B1 SENSE AMPLIFIER 有权
公开(公告)号：EP3200191B1
公开(公告)日：2018-12-05
申请号：EP16204024.0
申请日：2016-12-14
申请人： NXP USA, Inc.
发明人： Choy, Jon Scott
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1659 , G11C11/1693 , G11C11/1695 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C27/024 , G11C2013/0054 , G11C2013/0057 , G11C2213/74 , G11C2213/79
摘要： In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

5. 发明公开

EP3200191A1 SENSE AMPLIFIER 有权
公开(公告)号：EP3200191A1
公开(公告)日：2017-08-02
申请号：EP16204024.0
申请日：2016-12-14
申请人： NXP USA, Inc.
发明人： Choy, Jon Scott
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1659 , G11C11/1693 , G11C11/1695 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C27/024 , G11C2013/0054 , G11C2013/0057 , G11C2213/74 , G11C2213/79
摘要： In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.
摘要翻译：在非易失性存储器中，执行感测操作以读取非易失性（NV）元件的方法包括第一阶段和第二阶段。在第一阶段期间，NV元件经由感测路径晶体管耦合到放大器级的第一输入处的第一电容元件，并且参考单元经由参考感测路径晶体管耦合到第二输入处的第二电容元件放大器阶段。在第二阶段期间，NV元件经由感测路径晶体管耦合到第二电容元件，并且参考单元经由参考感测路径晶体管耦合到第一电容元件。在第一阶段期间，第一和第二电容性元件分别被初始化为表示NV元件和参考单元的状态的电压。在第二阶段，两个电压之间的电压差被放大。

6. 发明公开

EP3249655A1 NONVOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) SYSTEM HAVING A STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY AND A RESISTIVE MEMORY ARRAY 有权
标题翻译：具有静态随机存取存储器（SRAM）阵列和电阻存储器阵列的非易失性静态随机存取存储器（NVSRAM）系统
公开(公告)号：EP3249655A1
公开(公告)日：2017-11-29
申请号：EP17172930.4
申请日：2017-05-25
申请人： NXP USA, Inc.
发明人： Roy, Anirban , Sadd, Michael A. , Choy, Jon Scott
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00 , G11C11/419 , G11C27/02 , H01L27/11
CPC分类号： G11C14/0081 , G11C11/005 , G11C11/1673 , G11C11/419 , G11C13/004 , G11C27/024 , G11C2013/0042 , G11C2013/0045 , H01L27/1104
摘要： An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.
摘要翻译：集成电路（IC）器件包括静态随机存取存储器（SRAM）阵列和电阻式存储器（电阻式存储器）阵列。电阻式存储器阵列中的第一组可编程电阻元件用于存储来自SRAM阵列中的存储器单元的数据。读出放大器电路可以连接到SRAM阵列和电阻式存储器阵列。仲裁器被配置成断言电阻式存储器使能信号以将读出放大器电路耦合到电阻式存储器阵列并且在电阻式存储器读取操作期间将读出放大器电路与SRAM阵列解耦以及将读出放大器耦合到SRAM阵列并且在SRAM读取操作期间将读出放大器电路与电阻式存储器阵列解耦。

7. 发明公开

EP4435786A1 MEMORY WITH ONE-TIME PROGRAMMABLE (OTP) CELLS 审中-公开
公开(公告)号：EP4435786A1
公开(公告)日：2024-09-25
申请号：EP24164499.6
申请日：2024-03-19
申请人： NXP USA, Inc.
发明人： Roy, Anirban , Mahatme, Nihaar N. , Choy, Jon Scott
IPC分类号： G11C11/16 , G11C17/16 , G11C17/18 , G11C7/10 , G11C7/16
CPC分类号： G11C11/1675 , G11C17/18 , G11C7/1078 , G11C11/161 , G11C11/1677 , G11C11/1697 , G11C7/16 , G11C17/16
摘要： A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

8. 发明公开

EP4276837A1 TESTING DISRUPTIVE MEMORIES FOR METASTABLE CONDITIONS 审中-实审
公开(公告)号：EP4276837A1
公开(公告)日：2023-11-15
申请号：EP23172125.9
申请日：2023-05-08
申请人： NXP USA, Inc.
发明人： Strauss, Timothy , Choy, Jon Scott , Sadd, Michael A.
IPC分类号： G11C29/50 , G11C29/38 , G11C29/44 , G11C7/02
摘要： Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

9. 发明公开

EP4047606A3 MEMORY WITH SENSE AMPLIFIERS 审中-实审
公开(公告)号：EP4047606A3
公开(公告)日：2023-03-01
申请号：EP22152041.4
申请日：2022-01-18
申请人： NXP USA, Inc.
发明人： Sadd, Michael A. , Choy, Jon Scott
IPC分类号： G11C7/06 , G11C13/00 , G11C11/16
摘要： A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.

10. 发明公开

EP4047606A2 MEMORY WITH SENSE AMPLIFIERS 审中-实审
公开(公告)号：EP4047606A2
公开(公告)日：2022-08-24
申请号：EP22152041.4
申请日：2022-01-18
申请人： NXP USA, Inc.
发明人： Sadd, Michael A. , Choy, Jon Scott
IPC分类号： G11C7/06 , G11C13/00 , G11C11/16
摘要： A memory includes a pair of sense amplifiers where the pair of sense amplifiers perform a multiphase memory operation to read data from two memory cells. Each sense amplifier includes two current paths. During a first phase of the memory read operation, one of the two sense amplifiers provides current through both a first memory cell and a first reference cell and the other sense amplifier of the two provides current through both a second memory cell and a second reference cell. The reference cells each have different resistance values. During a second phase of the memory read operation, one of the sense amplifiers provides current through both of the first memory cell and the second reference cell and the second sense amplifier provides current through the second memory cell and the first reference cell.

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