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1. 发明公开

EP0776010A2 Improvements in or relating to integrated circuits 失效
标题翻译：在Bezug auf integrierte Schaltungen的Verbesserungenenenungenenen
公开(公告)号：EP0776010A2
公开(公告)日：1997-05-28
申请号：EP96308453.8
申请日：1996-11-21
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coffman, Tim M. , Syzdek, Ronald J. , Coots, Timothy J. , Truong, Phat C. , Lin, Sung-Wei
IPC分类号： G11C7/00
CPC分类号： G11C7/22
摘要： The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pules from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.
摘要翻译：本发明的方法防止了在高频禁用周期的瞬态电流，并且在最小延迟时间之后禁用DC电流路径，从而降低功耗。本发明包括延迟电路，其功能是防止在低于最小持续时间的间隔下出现芯片禁用时间的DC路径的禁用。结果是由于瞬态电流，内部电源总线上的不期望的电压降的数量减少。该方法检测在最小持续时间之前发生的外部芯片禁止脉冲，然后防止那些电源断开内部直流路径。同时，保持了芯片禁止信号的输出驱动器高阻抗功能。

2. 发明授权

EP0499110B1 Switch for use on an integrated circuit 失效
标题翻译：开关，可使用在集成电路中
公开(公告)号：EP0499110B1
公开(公告)日：1997-06-25
申请号：EP92101715.8
申请日：1992-02-03
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C. , Desai, Chirag A.
IPC分类号： H03K17/693 , G11C16/06
CPC分类号： H03K17/693 , G11C16/12 , H01L27/0248 , H03K2217/0018

3. 发明公开

EP0499110A3 Switch for use on an integrated circuit 失效
标题翻译：切换用于集成电路
公开(公告)号：EP0499110A3
公开(公告)日：1994-03-09
申请号：EP92101715.8
申请日：1992-02-03
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C. , Desai, Chirag A.
IPC分类号： H03K17/693 , G11C16/06
CPC分类号： H03K17/693 , G11C16/12 , H01L27/0248 , H03K2217/0018
摘要： A switching circuit for selectively coupling a first power supply (Vpp) to a power bus (24) includes a first input terminal (33) for connection to the first power supply (Vpp) and a means (34) for coupling said first input terminal (33) to a first node (A). A first transistor (36) has a first source/drain region coupled to the first node (A) and a second source/drain region coupled to the power bus (24). The first transistor (36) is on in response to a first control signal applied to its gate to couple the first node (A) to the power bus (24). A bias circuit (52,54,56) is coupled to the substrate (b) of the first transistor (36) to prevent forward biasing of a junction between its substrate and its second source/drain region when the first transistor (36) is on.
摘要翻译：用于选择性地将第一电源（Vpp）耦合到电源总线（24）的开关电路包括用于连接到第一电源（Vpp）的第一输入端子（33）和用于将所述第一输入端子（33）传送到第一节点（A）。第一晶体管（36）具有耦合到第一节点（A）的第一源极/漏极区域和耦合到电力总线（24）的第二源极/漏极区域。第一晶体管（36）响应于施加到其栅极的第一控制信号而导通，以将第一节点（A）耦合到电力总线（24）。偏置电路（52,54,56）耦合到第一晶体管（36）的衬底（b）以防止当第一晶体管（36）为第一晶体管（36）时其正向偏置其衬底与其第二源极/ 上。

4. 发明公开

EP0453812A3 Worldline driver circuit for nonvolatile memory cell array 失效
标题翻译：用于非易失性存储器单元阵列的世界线驱动电路
公开(公告)号：EP0453812A3
公开(公告)日：1992-12-16
申请号：EP91104995.5
申请日：1991-03-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C. , Ashmore, Benjamin H., Jr. , Steigler, Harvey J.
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/12 , G11C16/08
摘要： A circuit 22 for driving a wordline (WORDLINE) in a floating-gate-type nonvolatile memory cell array, including a read-driver subcircuit (PART A) for switching a positive read voltages (Vcc) and a program-driver subcircuit (PART B) for switching positive programming voltages (Vppsw,Vhssw). The circuit (22) also includes a subcircuit (T11) for switching negative erasing voltages (Vee). The read-driver subcircuit (PART A) may be constructed using relatively short-channel transistors (T1-5) for relatively high speed of operation when connected to high-capacitance wordlines (WORDLINE). On the other hand, the program-driver subcircuit (PART B) may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit (PART A). P-channel isolating transistors (T6,T7,T11) are used to isolate unused circuitry during operation. The program-driver circuit (PART B) includes a voltage translator subcircuit (TR) having a transistor configuration that lessens the probability that the breakdown voltages of those transistors (T12-19) will be exceeded.

5. 发明公开

EP0453812A2 Worldline driver circuit for nonvolatile memory cell array 失效
标题翻译： WortleitungstreiberschaltungfürnichtflüchtigesSpeicherzellenarray。
公开(公告)号：EP0453812A2
公开(公告)日：1991-10-30
申请号：EP91104995.5
申请日：1991-03-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C. , Ashmore, Benjamin H., Jr. , Steigler, Harvey J.
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/12 , G11C16/08
摘要： A circuit 22 for driving a wordline (WORDLINE) in a floating-gate-type nonvolatile memory cell array, including a read-driver subcircuit (PART A) for switching a positive read voltages (Vcc) and a program-driver subcircuit (PART B) for switching positive programming voltages (Vppsw,Vhssw). The circuit (22) also includes a subcircuit (T11) for switching negative erasing voltages (Vee).
The read-driver subcircuit (PART A) may be constructed using relatively short-channel transistors (T1-5) for relatively high speed of operation when connected to high-capacitance wordlines (WORDLINE). On the other hand, the program-driver subcircuit (PART B) may be constructed using relatively long-channel transistors and those long-channel transistors may be located on the memory chip remotely from the memory cells and from the read-driver circuit (PART A). P-channel isolating transistors (T6,T7,T11) are used to isolate unused circuitry during operation.
The program-driver circuit (PART B) includes a voltage translator subcircuit (TR) having a transistor configuration that lessens the probability that the breakdown voltages of those transistors (T12-19) will be exceeded.
摘要翻译：用于驱动浮栅型非易失存储单元阵列中的字线（WORDLINE）的电路22，包括用于切换正读电压（Vcc）和程序驱动器子电路（B部分）的读驱动器子电路（PART A））用于切换正编程电压（Vppsw，Vhssw）。电路（22）还包括用于切换负擦除电压（Vee）的分支电路（T11）。当连接到高电容字线（WORDLINE）时，读驱动器子电路（PART A）可以使用相对较短的沟道晶体管（T1-5）来构造，以实现较高的工作速度。另一方面，程序驱动器子电路（PART B）可以使用相对较长的沟道晶体管构成，并且这些长沟道晶体管可以远离存储器单元和读驱动电路（PART）位于存储器芯片上一个）。 P沟道隔离晶体管（T6，T7，T11）用于在运行期间隔离未使用的电路。程序驱动器电路（B部分）包括具有晶体管配置的电压转换器子电路（TR），其降低将超过这些晶体管的击穿电压（T12-19）的可能性。

6. 发明公开

EP0765037A2 Buffer for integrated circuit memories 失效
标题翻译：吹风机Speicherschaltungen
公开(公告)号：EP0765037A2
公开(公告)日：1997-03-26
申请号：EP96114778.2
申请日：1996-09-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coots, Timothy J. , Truong, Phat C. , Lin, Sung-Wei , Coffman, Tim M. , Robinson, Dennis R. , Syzdek, Ronald J.
IPC分类号： H03K19/0185 , H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361
摘要： The circuit of this invention includes a current-compensated output buffer (OBC) that decreases the output switching rate as the conditions for transient noise increase to provide operation at maximum speed during worst-case speed conditions while suppressing noise during worst-case noise conditions. Transistors (M35-M42) in the output pre-driver stages (15,16) are used to limit the output-stage (14) charge and discharge rate. These limiting pre-driver transistors (M35-M42) are controlled by a supply-voltage (V CC ) and temperature compensating circuit (BGC). Compensating circuit (BGC) includes long channel transistors configured to increase a reference current (I REF ) with temperature and to decrease that reference current (I REF ) with increase in supply voltage (V CC ), the compensating circuit (BGC) providing biasing currents (I REFN and I REFP ) to output stage (14).
摘要翻译：本发明的电路包括电流补偿输出缓冲器（OBC），其随着瞬态噪声条件的增加而降低输出开关频率，以在最差情况下的速度条件下以最大速度运行，同时抑制最坏情况下的噪声条件下的噪声。输出预驱动级（15,16）中的晶体管（M35-M42）用于限制输出级（14）的充放电速率。这些限制性预驱动晶体管（M35-M42）由电源电压（VCC）和温度补偿电路（BGC）控制。补偿电路（BGC）包括配置为随温度增加参考电流（IREF）并随着电源电压（VCC）增加而减小该参考电流（IREF）的长沟道晶体管，补偿电路（BGC）提供偏置电流（IREFN和 IREFP）到输出级（14）。

7. 发明公开

EP0436814A2 Method and apparatus for reading and programming electrically programmable memory cells 失效
标题翻译：的方法和装置，用于读取和编程电可编程存储单元。
公开(公告)号：EP0436814A2
公开(公告)日：1991-07-17
申请号：EP90122395.8
申请日：1990-11-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C.
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/26
摘要： Apparatus for decoding a plurality of electrically programmable memory cells (30-70) comprises an array source driver circuit (72) for selectively connecting a first terminal (140) of a selected memory cell (152) to a program bias voltage or to ground. A bit line driver circuit (94-100, 120) selectively connects a second terminal (154) of said selected memory cell (152) to ground or to a read sense node (115). Reading is performed by connecting the first terminal (140) to ground and the second terminal (154) to the read sense node (115). Programming is performed by connecting the first terminal (140) to the program bias voltage and the second terminal (154) to ground.
摘要翻译：设备，用于选择的存储单元（152）的第一端子（140）选择性地连接到一个编程偏置电压或接地解码电可编程存储单元的多个（30-70）阵列源驱动器电路（72）的包含。位线驱动器电路（94-100，120），选择性地连接所述的第二端（154）选择的存储单元（152）到地或以一读出结点（115）。读数进行通过连接所述第一终端（140）到地和所述第二终端（154）所读取的感测节点（115）。编程执行通过连接所述第一终端（140）到节目的偏置电压和所述第二端子（154）接地。

8. 发明公开

EP0765037A3 Buffer for integrated circuit memories 失效
标题翻译：缓冲存储器集成电路
公开(公告)号：EP0765037A3
公开(公告)日：1998-01-14
申请号：EP96114778.2
申请日：1996-09-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Coots, Timothy J. , Truong, Phat C. , Lin, Sung-Wei , Coffman, Tim M. , Robinson, Dennis R. , Syzdek, Ronald J.
IPC分类号： H03K19/0185 , H03K19/003
CPC分类号： H03K19/00384 , H03K19/00361
摘要： The circuit of this invention includes a current-compensated output buffer (OBC) that decreases the output switching rate as the conditions for transient noise increase to provide operation at maximum speed during worst-case speed conditions while suppressing noise during worst-case noise conditions. Transistors (M35-M42) in the output pre-driver stages (15,16) are used to limit the output-stage (14) charge and discharge rate. These limiting pre-driver transistors (M35-M42) are controlled by a supply-voltage (V CC ) and temperature compensating circuit (BGC). Compensating circuit (BGC) includes long channel transistors configured to increase a reference current (I REF ) with temperature and to decrease that reference current (I REF ) with increase in supply voltage (V CC ), the compensating circuit (BGC) providing biasing currents (I REFN and I REFP ) to output stage (14).

9. 发明授权

EP0453812B1 Worldline driver circuit for nonvolatile memory cell array 失效
标题翻译：用于非易失性存储器单元阵列的字线驱动器电路
公开(公告)号：EP0453812B1
公开(公告)日：1997-05-28
申请号：EP91104995.5
申请日：1991-03-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C. , Ashmore, Benjamin H., Jr. , Steigler, Harvey J.
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/12 , G11C16/08

10. 发明公开

EP0436814A3 Method and apparatus for reading and programming electrically programmable memory cells 失效
标题翻译：用于读取和编程电可编程存储器单元的方法和设备
公开(公告)号：EP0436814A3
公开(公告)日：1994-02-23
申请号：EP90122395.8
申请日：1990-11-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Schreck, John F. , Truong, Phat C.
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/26
摘要： Apparatus for decoding a plurality of electrically programmable memory cells (30-70) comprises an array source driver circuit (72) for selectively connecting a first terminal (140) of a selected memory cell (152) to a program bias voltage or to ground. A bit line driver circuit (94-100, 120) selectively connects a second terminal (154) of said selected memory cell (152) to ground or to a read sense node (115). Reading is performed by connecting the first terminal (140) to ground and the second terminal (154) to the read sense node (115). Programming is performed by connecting the first terminal (140) to the program bias voltage and the second terminal (154) to ground.
摘要翻译：用于解码多个电可编程存储器单元（30-70）的设备包括用于选择性地将所选存储器单元（152）的第一端子（140）连接至编程偏置电压或接地的阵列源极驱动器电路（72）。位线驱动器电路（94-100,120）选择性地将所述选定存储器单元（152）的第二端子（154）连接到地或连接到读取感测节点（115）。通过将第一端子（140）连接到地面并将第二端子（154）连接到读取感测节点（115）来执行读取。通过将第一端子（140）连接到编程偏压并且第二端子（154）接地来执行编程。

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