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1. 发明公开

EP0626659A1 Apparatus, system and method for distributed processing 失效
标题翻译： Vorrichtung，系统和Verfahren zur verteilten Datenverarbeitung。
公开(公告)号：EP0626659A1
公开(公告)日：1994-11-30
申请号：EP94303756.4
申请日：1994-05-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mahant-Shetti, Shivaling , Pawate, Basavaraj , Doddington, George R. , Smith, Derek
IPC分类号： G06F15/78
CPC分类号： G06F9/3879 , G06F15/7821
摘要： An active memory device 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding broad data and computational results. A broadcast memory 22 is also provided which includes rows and columns of storage locations for holding control instructions and computational arguments. A data path operable to apply selected computational arguments received from broadcast memory 22 to selected words of raw data received from data memory 20 and provide computational results in response. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the selected words of raw data and results between the data memory 20 and the data path 26, the transfer of the selected arguments from the broadcast memory 22 to the data path 26, and the application of the selected arguments to the selected words of raw data by data path 26.
摘要翻译：提供了一种有源存储器件14，其包括数据存储器20，数据存储器20包括用于保存广泛数据和计算结果的存储位置的行和列。还提供广播存储器22，其包括用于保持控制指令和计算参数的存储位置的行和列。数据路径，用于将从广播存储器22接收的所选计算参数应用于从数据存储器20接收的原始数据的选定字，并提供响应的计算结果。控制电路24可响应于从广播存储器22接收的控制指令来操作，以控制数据存储器20和数据通路26之间的原始数据和结果的选定字的传送，从广播存储器22传送所选参数到数据路径26，以及通过数据路径26将所选择的参数应用于原始数据的所选择的单词。

2. 发明公开

EP0629942A1 Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit 失效
标题翻译： Gerät，Systeme und Verfahren zurDurchführungeines speichereingebetteten这样的ALU。
公开(公告)号：EP0629942A1
公开(公告)日：1994-12-21
申请号：EP94303755.6
申请日：1994-05-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Pawate, Basavaraj , Mahant-Shetti, Shivaling S. , Doddington, George D. , Smith, Derek
IPC分类号： G06F7/48 , G06F15/409
CPC分类号： G06F7/575 , G06F9/3879 , G06F15/7821 , G06F17/30982 , G06F2207/4802 , G06F2207/4804
摘要： An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is operable to receive at least one word of data from data memory 20 and test the word against a preselected search test condition. Control circuitry 24 is operable in response to control instructions received from the broadcast memory 22 to control the transfer of the word of data from the data memory 20 to the search circuitry 26, 52 and the test of the word by the search circuitry 26, 52.
摘要翻译：提供了一种活动存储器14，其包括数据存储器20，数据存储器20包括用于保存数据的存储位置的行和列。提供广播存储器22，其包括用于保持控制指令的存储位置的行和列。提供了搜索电路26,52，其可操作以从数据存储器20接收至少一个数据字，并根据预选的搜索测试条件测试该字。控制电路24可响应于从广播存储器22接收的控制指令来操作，以控制从数据存储器20到搜索电路26,52的数据字的传送以及搜索电路26,52对字的测试。

3. 发明公开

EP0626650A1 Devices, systems and methods for implementing a Kanerva memory 失效
标题翻译： Geräte，Einrichtungen und Verfahren zur Implementierung eines Kanerva-Speichers。
公开(公告)号：EP0626650A1
公开(公告)日：1994-11-30
申请号：EP94303786.1
申请日：1994-05-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Smith, Derek , Mahant-Shetti, Shivaling , Pawate, Basavaraj , Doddington, George R. , Bean, Warren L.
IPC分类号： G06F15/409 , G06F12/02
CPC分类号： G06F17/30982 , G06F12/02
摘要： A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.
摘要翻译：提供存储器系统10，其包括耦合到处理器12的处理器12和有源存储器设备14.活动存储器14包括用于存储多个可能地址的第一存储器20和用于存储从处理器接收的实际地址的第二存储器22 提供电路26，用于根据存储在第二存储器22中的实际地址的函数来识别存储在第一存储器20中的可能地址中的至少一个活动地址。

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