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1. 发明公开

EP0375226A2 An seu hardened memory cell 失效
标题翻译： Gegen weiche FehlerbroadstandsfähigeSpeicherzelle。
公开(公告)号：EP0375226A2
公开(公告)日：1990-06-27
申请号：EP89312867.8
申请日：1989-12-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Houston, Theodore W. , Blake, Terence G. W.
IPC分类号： G11C5/00 , G11C11/412 , H01L27/11
CPC分类号： G11C5/005 , G11C11/4125
摘要： A memory cell is disclosed comprising cross-coupled inverters including gated diodes in the cross-coupling.
摘要翻译：公开了一种存储器单元，其包括在交叉耦合中包括门控二极管的交叉耦合的反相器。

2. 发明授权

EP0357982B1 Memory cell with improved single event upset rate reduction circuitry 失效
标题翻译：具有用于减少杂波各个事件的电路的存储器单元。
公开(公告)号：EP0357982B1
公开(公告)日：1995-03-01
申请号：EP89114653.2
申请日：1989-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Houston, Theodore W.
IPC分类号： G11C5/00 , G11C11/412 , H03K3/356
CPC分类号： G11C5/005 , G11C11/4125

3. 发明公开

EP0840453A2 An output buffer 失效
标题翻译： Ausgangspuffer
公开(公告)号：EP0840453A2
公开(公告)日：1998-05-06
申请号：EP97118708.3
申请日：1997-10-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Andresen, Bernhard
IPC分类号： H03K19/003
CPC分类号： H03K19/00315
摘要： An output buffer includes a pair of P-channel transistors and two cascode pull-down N-channel transistors to drive an output node. The output pull-up transistor (Q6) has the gate thereof connected through a P-channel control transistor (Q5) to an input driving signal. The control signal is isolated from the output node by a shunt P-channel transistor (Q4) which only conducts during overvoltage conditions. During normal operation, the control transistor (Q5) is maintained in a conductive state to allow the gate of the output pull-up transistor (Q6) to be pulled high and low. During an overvoltage condition, the shunt P-channel transistor (Q4) connected between the output node and the control transistor is turned on to effectively turn off the control transistor. The output P-channel transistor (Q6) is protected from excess voltages across the gate oxide when initially coming out of the hiZ state with a logic high signal on the input. This is facilitated by pulling the gate thereof low to a voltage above ground and then pulling the gate fully to ground when the voltage on the output node falls to below the supply voltage. This is provided by a NAND gate structure (120,122,124,128) that disposes a limiting P-channel transistor (128) in series with the gate of the P-channel pull-up transistor (Q6) to prevent it from going to a full logic low level. When the voltage on the output is pulled down by the shunt P-channel transistor (Q4), this will then bypass the limiting P-channel transistor (128) in the NAND gate and pull the gate of the P-channel pull-up transistor (Q6) down to the full low logic level.
摘要翻译：输出缓冲器包括一对P沟道晶体管和两个共源共栅下拉N沟道晶体管，以驱动输出节点。输出上拉晶体管（Q6）的栅极通过P沟道控制晶体管（Q5）连接到输入驱动信号。控制信号通过仅在过电压条件下导通的并联P沟道晶体管（Q4）与输出节点隔离。在正常操作期间，控制晶体管（Q5）保持导通状态，以使输出上拉晶体管（Q6）的栅极被拉高和低电平。在过电压状态下，连接在输出节点和控制晶体管之间的并联P沟道晶体管（Q4）导通，有效地关断控制晶体管。输出P沟道晶体管（Q6）在初始从输入的逻辑高电平信号输出hiZ状态时，可防止栅极氧化物上的多余电压。这通过将栅极拉低到高于地电压，然后当输出节点上的电压下降到电源电压以下时将栅极完全拉到地，便于此。这由NAND门结构（120,122,124,128）提供，其配置与P沟道上拉晶体管（Q6）的栅极串联的限制P沟道晶体管（128），以防止其进入完全逻辑低电平。当输出上的电压被并联P沟道晶体管（Q4）下拉时，这将旁路NAND门中的限制P沟道晶体管（128），并将P沟道上拉晶体管的栅极拉（Q6）降至全低逻辑电平。

4. 发明公开

EP0357982A2 Memory cell with improved single event upset rate reduction circuitry 失效
标题翻译： Speicherzelle mit einer Schaltung zur Reduzierung von Unordnungseinzelereignissen。
公开(公告)号：EP0357982A2
公开(公告)日：1990-03-14
申请号：EP89114653.2
申请日：1989-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Houston, Theodore W.
IPC分类号： G11C5/00 , G11C11/412 , H03K3/356
CPC分类号： G11C5/005 , G11C11/4125
摘要： The rate of single event upset in a bi-stable logic device (2) is reduced by circuitry including a pair of active devices (22, 24) in the cross-coupling between a pair of inverters (4, 5). The active devices (22, 24) are controlled by voltages internal to the bi-stable logic device (2) such that writing into the device (2) is not significantly slowed.
摘要翻译：双稳态逻辑器件（2）中的单事件扰乱的速率由包括一对反相器（4,5）之间的交叉耦合中的一对有源器件（22,24）的电路减小。有源器件（22,24）由双稳态逻辑器件（2）内部的电压控制，使得对器件（2）的写入不会明显减慢。

5. 发明公开

EP0357980A3 A memory cell with capacitance for single event upset protection 失效
标题翻译：具有单电池保护电容的存储单元
公开(公告)号：EP0357980A3
公开(公告)日：1991-01-16
申请号：EP89114650.8
申请日：1989-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Houston, Theodore W.
IPC分类号： H01L27/11 , H01L27/108
CPC分类号： G11C5/005 , G11C11/4125 , H01L27/1104 , Y10S257/904
摘要： A compact capacitor (24, 26) for use in a small memory cell in high density memories is disclosed. Such a capacitor (24, 26) in the cross-coupling of cross-coupled inverters (4, 5) in the memory cell improves single event upset hardness. The subject capacitor (24, 26) in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.

6. 发明公开

EP0357980A2 A memory cell with capacitance for single event upset protection 失效
标题翻译： Speicherzelle mit Kondensator als Schutz gegen Einzelereignisse。
公开(公告)号：EP0357980A2
公开(公告)日：1990-03-14
申请号：EP89114650.8
申请日：1989-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Houston, Theodore W.
IPC分类号： H01L27/11 , H01L27/108
CPC分类号： G11C5/005 , G11C11/4125 , H01L27/1104 , Y10S257/904
摘要： A compact capacitor (24, 26) for use in a small memory cell in high density memories is disclosed. Such a capacitor (24, 26) in the cross-coupling of cross-coupled inverters (4, 5) in the memory cell improves single event upset hardness. The subject capacitor (24, 26) in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.
摘要翻译：公开了一种用于高密度存储器中的小存储单元的小型电容器（24,26）。在存储单元中交叉耦合的反相器（4,5）的交叉耦合中的这种电容器（24,26）改善了单事件镦粗硬度。在其优选实施例中的目标电容器（24,26）是具有与电容器通道的n +和p +连接的MOS电容器，以便为正和负电容器栅极电压保持相对较高的电容。

7. 发明公开

EP0840453A3 An output buffer 失效
标题翻译：一个输出缓冲区
公开(公告)号：EP0840453A3
公开(公告)日：1998-05-13
申请号：EP97118708.3
申请日：1997-10-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Andresen, Bernhard
IPC分类号： H03K19/003
CPC分类号： H03K19/00315
摘要： An output buffer includes a pair of P-channel transistors and two cascode pull-down N-channel transistors to drive an output node. The output pull-up transistor (Q6) has the gate thereof connected through a P-channel control transistor (Q5) to an input driving signal. The control signal is isolated from the output node by a shunt P-channel transistor (Q4) which only conducts during overvoltage conditions. During normal operation, the control transistor (Q5) is maintained in a conductive state to allow the gate of the output pull-up transistor (Q6) to be pulled high and low. During an overvoltage condition, the shunt P-channel transistor (Q4) connected between the output node and the control transistor is turned on to effectively turn off the control transistor. The output P-channel transistor (Q6) is protected from excess voltages across the gate oxide when initially coming out of the hiZ state with a logic high signal on the input. This is facilitated by pulling the gate thereof low to a voltage above ground and then pulling the gate fully to ground when the voltage on the output node falls to below the supply voltage. This is provided by a NAND gate structure (120,122,124,128) that disposes a limiting P-channel transistor (128) in series with the gate of the P-channel pull-up transistor (Q6) to prevent it from going to a full logic low level. When the voltage on the output is pulled down by the shunt P-channel transistor (Q4), this will then bypass the limiting P-channel transistor (128) in the NAND gate and pull the gate of the P-channel pull-up transistor (Q6) down to the full low logic level.
摘要翻译：输出缓冲器包括一对P沟道晶体管和两个共源共栅下拉N沟道晶体管以驱动输出节点。输出上拉晶体管（Q6）的栅极通过P沟道控制晶体管（Q5）连接到输入驱动信号。控制信号通过只在过压条件下导通的并联P沟道晶体管（Q4）与输出节点隔离。在正常操作期间，控制晶体管（Q5）保持导通状态，以允许输出上拉晶体管（Q6）的栅极被拉高和拉低。在过压情况下，连接在输出节点和控制晶体管之间的分流P沟道晶体管（Q4）导通，有效关断控制晶体管。输出P沟道晶体管（Q6）在开始从输入端输出逻辑高电平信号到hiZ状态时，会受到栅氧化层两端过电压的保护。通过将其栅极拉至低于地电压，然后当输出节点上的电压下降至低于电源电压时将栅极完全拉至接地，便于实现这一点。这是由一个NAND门结构（120,122,124,128）提供的，它将一个限制P沟道晶体管（128）与P沟道上拉晶体管（Q6）的栅极串联，以防止其进入全逻辑低电平。当输出端上的电压被分流P沟道晶体管（Q4）拉低时，这将绕过NAND门中的限制P沟道晶体管（128），并拉动P沟道上拉晶体管（Q6）降至完全低逻辑电平。

8. 发明授权

EP0450283B1 SOI layout for low resistance gate 失效
标题翻译： SOI布局栅极低电阻
公开(公告)号：EP0450283B1
公开(公告)日：1996-09-18
申请号：EP91101770.5
申请日：1991-02-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Houston, Theodore W. , Blake, Terence G. W.
IPC分类号： H01L27/12
CPC分类号： H01L27/1203

9. 发明授权

EP0375226B1 An seu hardened memory cell 失效
标题翻译：软错误耐存储器单元
公开(公告)号：EP0375226B1
公开(公告)日：1996-03-06
申请号：EP89312867.8
申请日：1989-12-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Houston, Theodore W. , Blake, Terence G. W.
IPC分类号： G11C5/00 , G11C11/412 , H01L27/11
CPC分类号： G11C5/005 , G11C11/4125

10. 发明授权

EP0357980B1 A memory cell with capacitance for single event upset protection 失效
标题翻译：存储电容器作为对单一事件的保护。
公开(公告)号：EP0357980B1
公开(公告)日：1995-01-11
申请号：EP89114650.8
申请日：1989-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Blake, Terence G. W. , Houston, Theodore W.
IPC分类号： H01L27/11 , H01L27/108
CPC分类号： G11C5/005 , G11C11/4125 , H01L27/1104 , Y10S257/904

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