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1. 发明公开

EP3306479A1 MEMORY STRUCTURE COMPRISING SCRATCHPAD MEMORY 审中-公开
标题翻译：包含SCRATCHPAD存储器的存储器结构
公开(公告)号：EP3306479A1
公开(公告)日：2018-04-11
申请号：EP16192581.3
申请日：2016-10-06
申请人： Stichting IMEC Nederland , IMEC VZW
发明人： CATTHOOR, Francky , SETOAIN RODRIGO, Javier , GOMEZ, Jose Ignacio , PAPASTERGIOU, Thomas , TENLLADO, Christian , XYDIS, Sotiris , BALOUKAS, Christos , DAS, Anup Kumar , HARTMANN, Matthias , SOUDRIS, Dimitrios
IPC分类号： G06F12/0897 , G06F12/1009 , G06F12/08 , G06F12/0864 , G06F12/02 , G06F9/50
CPC分类号： G06F12/1054 , G06F12/023 , G06F12/08 , G06F12/0811 , G06F12/0864 , G06F12/0897 , G06F12/1009 , G06F12/122 , G06F12/128 , G06F2212/1016 , G06F2212/2515 , G06F2212/283 , G06F2212/502 , G06F2212/621 , G06F2212/652 , Y02D10/13
摘要： The present invention relates to a memory hierarchy for a system-in-package. The memory hierarchy is directly connectable to a processor (10) via a memory management unit arranged for translating a virtual address sent by said processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster (21) having one or more banks of scratchpad memory. The memory structure comprises a first data access controller (31) arranged for managing one or more of said banks of scratchpad memory of at least one of said clusters of at least said L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking, for each received physical address, if said physical address is present in said one or more banks of said at least one cluster of at least said L1 memory array and, if so, as a part of said managing, for forwarding a data request to one or more banks of scratchpad memory where said physical address is required, and if not, for forwarding said physical address to a cache controller (40) steering said data cache memory.
摘要翻译：本发明涉及用于系统级封装的存储器层次结构。存储器层级经由存储器管理单元可直接连接到处理器（10），所述存储器管理单元被布置用于将由所述处理器发送的虚拟地址转换为物理地址。存储器层次结构具有数据高速缓冲存储器和具有至少一个L1存储器阵列的存储器结构，所述L1存储器阵列包括具有一个或多个暂存器存储器组的至少一个簇（21）。所述存储器结构包括第一数据存取控制器（31），所述第一数据存取控制器（31）被安排用于管理至少所述L1存储器阵列的所述群集中的至少一个的所述暂存器存储器的所述存储体中的一者或一者以上，所述数据端口包括用于接收并且被安排用于针对每个接收到的物理地址检查所述物理地址是否存在于所述至少一个L1存储器阵列的所述至少一个簇的所述一个或多个存储体中，并且如果存在，作为所述管理的一部分，向需要所述物理地址的暂存器存储器的一个或多个存储体提供数据请求，如果不是，则向所述物理地址转发给高速缓存控制器（40）以转向所述数据高速缓存存储器。

2. 发明公开

EP2681740A1 LOCAL WRITE AND READ ASSIST CIRCUITRY FOR MEMORY DEVICE 失效转让
标题翻译：当地写作和阅读辅助电路给存储设备
公开(公告)号：EP2681740A1
公开(公告)日：2014-01-08
申请号：EP12712598.7
申请日：2012-03-05
申请人： Stichting IMEC Nederland , Katholieke Universiteit Leuven
发明人： SHARMA, Vibhu , COSEMANS, Stefan , DEHAENE, Wim , CATTHOOR, Francky , ASHOUEI, Maryam , HUISKEN, Jos
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/18 , G11C11/412
摘要： Memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

3. 发明授权

EP2681740B1 LOCAL WRITE AND READ ASSIST CIRCUITRY FOR MEMORY DEVICE 失效转让
标题翻译：当地写作和阅读辅助电路给存储设备
公开(公告)号：EP2681740B1
公开(公告)日：2016-10-19
申请号：EP12712598.7
申请日：2012-03-05
申请人： Stichting IMEC Nederland , Katholieke Universiteit Leuven
发明人： SHARMA, Vibhu , COSEMANS, Stefan , DEHAENE, Wim , CATTHOOR, Francky , ASHOUEI, Maryam , HUISKEN, Jos
IPC分类号： G11C7/18 , G11C11/412 , G11C11/419
CPC分类号： G11C11/419 , G11C7/18 , G11C11/412

4. 发明授权

EP2998756B1 SIMULATION OF PHOTOVOLTAIC MODULES 有权
标题翻译：光伏模块的模拟
公开(公告)号：EP2998756B1
公开(公告)日：2017-07-05
申请号：EP15185293.6
申请日：2015-09-15
申请人： IMEC VZW , Katholieke Universiteit Leuven
发明人： GOVERDE, Hans , CATTHOOR, Francky , DUBEY, Vikas , POORTMANS, Jef , BAERT, Christiaan
IPC分类号： G01R31/40
CPC分类号： G06F17/5009 , G06F17/10 , H02S50/00 , H02S50/10

5. 发明公开

EP3147908A1 LEVEL 1 MEMORY STRUCTURE WITH A NON-VOLATILE MEMORY AND A BUFFER 审中-公开
标题翻译：与非易失性存储器，储存槽第一阶段L1存储器结构
公开(公告)号：EP3147908A1
公开(公告)日：2017-03-29
申请号：EP15186601.9
申请日：2015-09-24
申请人： IMEC VZW
发明人： CATTHOOR, Francky , RAGHAVAN, Praveen , HARTMANN, Matthias , KOMALAN PERUMKUNNIL, Manu , GÓMEZ, José Ignacio , TENLLADO, Christian
IPC分类号： G11C7/10 , G06F12/08 , G11C11/16
CPC分类号： G06F12/0811 , G06F3/0611 , G06F3/0656 , G06F3/0685 , G06F3/0688 , G06F8/41 , G06F8/452 , G06F9/30036 , G06F9/38 , G06F12/0862 , G06F12/0893 , G06F12/0897 , G06F13/1657 , G06F13/1673 , G06F15/781 , G06F15/7846 , G06F2212/1016 , G06F2212/222 , G06F2212/454 , G06F2212/601 , G06F2212/6028 , G11C7/10 , G11C11/165 , G11C11/1673 , G11C11/1675
摘要： The present invention relates to a memory hierarchy being directly connectable to a processor, said memory hierarchy having at least a Level 1, hereinafter termed L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB), said buffer structure comprising a plurality of interconnected wide registers with an asymmetric organization, wider towards said non-volatile memory unit than towards a data path connectable to said processor, said buffer structure and said non-volatile memory unit arranged for being directly connectable to said processor so that data words are selectable to be read or written by said processor.
摘要翻译：本发明涉及一种存储器层级直接连接到处理器，所述具有至少一个第1级，其包括非易失性存储器单元为L1数据存储器和缓冲结构称为L1存储器结构之后开始（L1 VWB存储器层级），所述缓冲结构包括与在不对称组织互连宽寄存器复数，抗蚀剂对所述非易失性存储器单元比朝向连接到所述处理器，所述缓冲结构和被布置为直接地连接所述非易失性存储器单元的数据路径所述处理器象数据字被选择以进行读取或由所述处理器写入。

6. 发明公开

EP4351295A1 A 3D INTEGRATED CIRCUIT 审中-公开
公开(公告)号：EP4351295A1
公开(公告)日：2024-04-10
申请号：EP22200294.1
申请日：2022-10-07
申请人： Imec VZW , Katholieke Universiteit Leuven KU Leuven Research & Development
发明人： CATTHOOR, Francky , ABDI, Dawit Burusie
IPC分类号： H10B10/00 , H01L27/02 , H01L27/06
摘要： According to an aspect there is provided a 3D IC comprising: a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit. The 3D IC further comprises: pull-up and pull-down voltage rails routed vertically through the stack of bit cells and connected to each bit cell of the stack; and first and second word lines routed vertically through the stack of bit cells and connected to each bit cell of the stack of bit cells.

7. 发明授权

EP3142153B1 RECONFIGURABLE PHOTOVOLTAIC MODULE 有权
公开(公告)号：EP3142153B1
公开(公告)日：2020-04-01
申请号：EP15184967.6
申请日：2015-09-12
申请人： IMEC VZW
发明人： BAKA, Maria-Iro , CATTHOOR, Francky
IPC分类号： H01L31/02

8. 发明授权

EP2628244B1 DESIGN AND CONTROL OF MULTI-TEMPERATURE MICRO-OVEN FOR MEMS DEVICES 有权
标题翻译：设计和多温MICRO炉MEMS设备的控制
公开(公告)号：EP2628244B1
公开(公告)日：2016-08-17
申请号：EP11782075.3
申请日：2011-10-11
申请人： IMEC VZW , Katholieke Universiteit Leuven
发明人： MUNAGA, Satyakiran N. , CATTHOOR, Francky
IPC分类号： H03H9/02 , H03H9/08 , H03L1/04
CPC分类号： H03L1/04 , H03H9/02448 , H03H9/08

9. 发明公开

EP3506132A1 SIMULATION OF PHOTOVOLTAIC SYSTEMS 审中-公开
公开(公告)号：EP3506132A1
公开(公告)日：2019-07-03
申请号：EP17210740.1
申请日：2017-12-27
申请人： IMEC vzw , Katholieke Universiteit Leuven
发明人： CATTHOOR, Francky , BAKA, Maria-Iro , MANGANIELLO, Patrizio
IPC分类号： G06F17/50 , G05F1/67 , H01L31/04 , H02S50/10 , H02J3/38
摘要： A method (20) for generating/ updating a database of current-voltage characteristic curves is disclosed. This method comprises simulating (25), for at least one combination of a topology of a photovoltaic cell group, an internal cell temperature(s) and a cell irradiation(s), a model of the photovoltaic cell group to provide a current-voltage characteristic curve representative of that combination, and clustering (24) the current-voltage characteristic curves to identify at least one plurality of similar current-voltage characteristic curves. The method also comprises generating (26) a many-to-one mapping in the database to map query requests that correspond to each of the at least one plurality of similar current-voltage characteristic curves onto a single representative current-voltage characteristic curve for that plurality of similar current-voltage characteristic curves, each query request identifying a topology of a photovoltaic cell group, at least one internal temperature for the photovoltaic cells in the photovoltaic cell group and at least one cell irradiation for the photovoltaic cells in the photovoltaic cell group.

10. 发明公开

EP3142153A1 RECONFIGURABLE PHOTOVOLTAIC MODULE 有权
标题翻译： NEUKONFIGURIERBARES PHOTOVOLTAIKMODUL
公开(公告)号：EP3142153A1
公开(公告)日：2017-03-15
申请号：EP15184967.6
申请日：2015-09-12
申请人： IMEC VZW
发明人： BAKA, Maria-Iro , CATTHOOR, Francky
IPC分类号： H01L31/02
摘要： The present invention relates to a photovoltaic module (1) comprising a grid of photovoltaic cells, non-reconfigurable interconnects forming cell strings (5), and reconfigurable interconnects (6). Each cell string (5) comprises at least four cells connected in series, the first and the last cell being located on the same edge of the grid, the last cell being adjacent to a first cell of an adjacent cell string and/or vice versa. The reconfigurable interconnects (6) are adapted for interconnecting the cell strings (5) such that a global photovoltaic string consisting of an electrical series connecting the cell strings (5) can be established, and for establishing a parallel circuit of at least two adjacent cell strings (5). The reconfigurable interconnects (6) are adapted for receiving a control signal from a controller for forming parallel, serial and/or hybrid connections of the cell strings (5) to cluster matching cells under nonuniform irradiation.
摘要翻译：本发明涉及一种包括光伏电池格栅，形成电池串（5）的不可重构互连和可重配置互连（6））的光伏组件（1）。每个单元串（5）包括串联连接的至少四个单元，第一单元和最后一个单元位于网格的相同边缘上，最后单元与相邻单元串的第一单元相邻，和/或反之亦然。可重配置互连（6）适于互连电池串（5），使得可以建立由连接电池串（5）的电串联组成的全局光伏串，并且用于建立至少两个相邻电池的并联电路字符串（5）。可重配置互连（6）适于从控制器接收控制信号，用于在不均匀照射下形成单元串（5）到集束匹配单元的并行，串行和/或混合连接。

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