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1. 发明授权

EP2824657B1 POINT TO MULTI-POINT CLOCK-FORWARDED SIGNALING FOR LARGE DISPLAYS 有权转让
公开(公告)号：EP2824657B1
公开(公告)日：2019-04-24
申请号：EP14171817.1
申请日：2014-06-10
申请人： Samsung Display Co., Ltd.
发明人： Amirkhany, Amir , Jaffari, Nasrin
IPC分类号： G09G5/00 , H04N5/04 , H03K19/003

2. 发明公开

EP2830214A3 PVT tolerant differential circuit 有权转让
标题翻译： PVT容差微分电路
公开(公告)号：EP2830214A3
公开(公告)日：2015-06-10
申请号：EP14176819.2
申请日：2014-07-11
申请人： Samsung Display Co., Ltd.
发明人： Hekmat, Mohammad , Amirkhany, Amir
IPC分类号： H03F3/45 , H03K5/08 , H04L25/06 , H04L25/49
CPC分类号： H03F3/45183 , H03F2200/453 , H03F2203/45048 , H03F2203/45244 , H04L25/0272 , H04L25/4919
摘要： An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.
摘要翻译：一种自动校准的差分放大器，包括：输入级差分放大器，被配置为接收输入差分信号，差分放大输入差分信号以生成输入级输出差分信号，并且具有输入级偏置电流; 以及配置成响应于过程或环境变化自动校准输入级偏置电流的复制级差分放大器。差分放大器可以被包括在例如比较器和多级接收器中。

3. 发明公开

EP3537610A2 HYBRID HALF/QUARTER-RATE DECISION FEEDBACK EQUALIZER AND DISPLAY INCLUDING HYBRID HALF/QUARTER-RATE DECISION FEEDBACK EQUALIZER 无效转让
公开(公告)号：EP3537610A2
公开(公告)日：2019-09-11
申请号：EP19160874.4
申请日：2019-03-05
申请人： Samsung Display Co., Ltd
发明人： JOSE, Anup P. , Amirkhany, Amir , HEKMAT, Mohammad
IPC分类号： H03M9/00 , H04L7/033 , H04L25/03 , H04L27/01
摘要： A two-stage decision feedback equalizer for receiving serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer comprises a first stage, comprising a half-rate predictive decision feedback equalizer having: an analog input connected to the analog input of the two-stage decision feedback equalizer, a first digital output, and a second digital output. The two-stage decision feedback equalizer further comprises a second stage, comprising: a first flip flop having a data input connected to the first digital output, a second flip flop having a data input connected to the first digital output, a third flip flop having a data input connected to the second digital output, and a fourth flip flop having a data input connected to the second digital output. The first stage is in a first clock domain configured to operate with a first clock at a frequency equal to one half of the first data rate. The second stage is in a second clock domain configured to operate with a second clock at a frequency equal to one quarter of the first data rate.

4. 发明授权

EP2869518B1 A body-biased slicer design for predictive decision feedback equalizers 有权转让
公开(公告)号：EP2869518B1
公开(公告)日：2018-05-23
申请号：EP14189173.9
申请日：2014-10-16
申请人： Samsung Display Co., Ltd.
发明人： Hekmat, Mohammad , Amirkhany, Amir
IPC分类号： G09G5/00 , H03M1/00 , H03M1/70 , H04L25/03
CPC分类号： H04L25/03057 , G09G5/006 , G09G2310/0297 , G09G2330/021 , H03M1/002 , H03M1/70 , H04L25/03146 , H04L25/03878
摘要： A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.

5. 发明授权

EP2858243B1 An offset cancellation technique for duty cycle correction loops 有权转让
公开(公告)号：EP2858243B1
公开(公告)日：2019-03-13
申请号：EP14185883.7
申请日：2014-09-23
申请人： Samsung Display Co., Ltd.
发明人： Amirkhany, Amir , Hekmat, Mohammad
IPC分类号： H03K5/156 , H03K3/017

6. 发明公开

EP2824657A1 Point to multi-point clock-forwarded signaling for large displays 有权转让
标题翻译： P t igen igen igen igen
公开(公告)号：EP2824657A1
公开(公告)日：2015-01-14
申请号：EP14171817.1
申请日：2014-06-10
申请人： Samsung Display Co., Ltd.
发明人： Amirkhany, Amir , Jaffari, Nasrin
IPC分类号： G09G5/00 , H04N5/04 , H03K19/003
CPC分类号： H04L7/0012 , G09G5/008 , G09G2320/0693 , G09G2370/08 , H04L7/0338 , H04L43/087 , H04N5/04
摘要： A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
摘要翻译：用于将采样率时钟与数据一起转发的系统。在一个实施例中，采样率时钟由发射机连同数据发送到一个或多个接收机。接收机使用接收到的采样时钟对接收到的数据进行采样。发射机中的延迟调整电路使用在接收机和发射机之间的后向通道中实现的延迟误差检测和校正来调整每个发送的数据流的延迟。

7. 发明公开

EP2858243A1 An offset cancellation technique for duty cycle correction loops 有权转让
标题翻译： OffsetunterdrückungstechnikfürDienstzykluskorrekturschleifen
公开(公告)号：EP2858243A1
公开(公告)日：2015-04-08
申请号：EP14185883.7
申请日：2014-09-23
申请人： Samsung Display Co., Ltd.
发明人： Amirkhany, Amir , Hekmat, Mohammad
IPC分类号： H03K5/156
CPC分类号： H03K3/017 , H03K5/1565
摘要： An electronic device (300) includes a clock (302) configured to transmit a first clock signal (CKIN) and a second clock signal (/CKIN) for operation of the electronic device; a duty cycle corrector (304, 308, 310) coupled to the clock (302) to correct a duty cycle of the first and second clock signals, the duty cycle corrector (304, 308, 310) being configured to: assign and store a first duty cycle correction code in response to the first clock signal (CKIN); assign and store a second duty cycle correction code in response to the second clock signal (/CKIN); calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.
摘要翻译：电子设备（300）包括：时钟（302），被配置为发送用于电子设备操作的第一时钟信号（CKIN）和第二时钟信号（/ CKIN）; 占空比校正器（304,308,310），其耦合到所述时钟（302）以校正所述第一和第二时钟信号的占空比，所述占空比校正器（304,308,310）被配置为：分配和存储响应于第一时钟信号（CKIN）的第一占空比校正码; 响应于第二时钟信号（/ CKIN）分配和存储第二占空比校正码; 基于第一和第二占空比校正码计算偏移码; 并且将偏移代码与占空比校正操作的结果否定。

8. 发明公开

EP2797231A1 Mismatched differential circuit 有权转让
标题翻译： Unterschiedliche Differenzschaltung
公开(公告)号：EP2797231A1
公开(公告)日：2014-10-29
申请号：EP14165501.9
申请日：2014-04-22
申请人： Samsung Display Co., Ltd.
发明人： Hekmat, Mohammad , Amirkhany, Amir
IPC分类号： H03F3/45 , H03K5/08
CPC分类号： H03F3/45179 , H03F3/45183 , H03K5/082 , H04L25/4917
摘要： A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.
摘要翻译：一种差分放大器，包括：包括第一晶体管的第一放大器支路和包括第二晶体管的第二放大器支路。这里，第一晶体管被配置为具有与第二晶体管的体电势不同的体积电位。第一放大器支路和第二放大器支路一起可以被配置为差分放大接收的差分输入信号。差分放大器可以被配置为具有输入偏移电压，其对应于第一晶体管的体电势与第二晶体管的体电势之间的差。差分放大器可以在比较器的输入级。

9. 发明授权

EP2902997B1 A system for relayed data transmission in a high-speed serial link in a display 有权转让
公开(公告)号：EP2902997B1
公开(公告)日：2019-01-16
申请号：EP15153167.0
申请日：2015-01-30
申请人： Samsung Display Co., Ltd.
发明人： Amirkhany, Amir , Xiong, Wei
IPC分类号： H04L25/02 , G09G3/20 , G09G3/36

10. 发明授权

EP2830214B1 PVT tolerant differential circuit 有权转让
公开(公告)号：EP2830214B1
公开(公告)日：2018-11-21
申请号：EP14176819.2
申请日：2014-07-11
申请人： Samsung Display Co., Ltd.
发明人： Hekmat, Mohammad , Amirkhany, Amir
IPC分类号： H03F3/45 , H03K5/08 , H04L25/06 , H04L25/49
CPC分类号： H03F3/45183 , H03F2200/453 , H03F2203/45048 , H03F2203/45244 , H04L25/0272 , H04L25/4919
摘要： An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.

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