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1. 发明公开

EP1434147A2 Method for increasing average storage capacity in a bit-mapped tree-based storage 审中-公开
标题翻译：方法zurErhöhungder durchschnittlichenSpeicherkapazität在einem bitgeordneten baumbasierten Speicher
公开(公告)号：EP1434147A2
公开(公告)日：2004-06-30
申请号：EP03257664.7
申请日：2003-12-05
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Rajgopal, Suresh , Richardson, Nicholas Julian
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06F17/30625 , H04L45/00 , H04L45/54 , H04L45/7457 , Y10S707/922 , Y10S707/99933
摘要： Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and/or replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoded allows variable length prefix portions to be encoded.
摘要翻译：位映射的多位特里内的稀疏分布前缀通过以下方式进行压缩：通过明确编码前缀部分的父表项替换单个前缀结束节点终止的单个条目表字符串; 用只有两个端节点或只有一个端节点和一个内部节点替换一个表，其中单个父表条目明确地编码前缀部分; 在通常由内部节点占用的表位置处使用单个压缩子条目替换两个端节点并且明确地编码前缀部分; 和/或用位于表端的仅限前缀的条目替换多个端节点来明确地编码多个前缀的部分。每次搜索表时，默认读取压缩子条目和仅前缀条目（如果存在）。编码的运行长度允许编码可变长度前缀部分。

2. 发明公开

EP1434148A3 Apparatus and method of implementing a multi-bit trie algorithmic network search engine 有权
标题翻译：设备和方法实现多bitgeordneten算法的网络搜索引擎
公开(公告)号：EP1434148A3
公开(公告)日：2008-01-09
申请号：EP03257666.2
申请日：2003-12-05
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Rajgopal, Suresh , Richardson, Nicholas Julian
IPC分类号： G06F17/30 , H04L12/56
CPC分类号： H04L45/54
摘要： A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.

3. 发明公开

EP1434147A3 Method for increasing average storage capacity in a bit-mapped tree-based storage 审中-公开
标题翻译：在基于树的记忆bitgeordneten提高平均存储容量的方法，
公开(公告)号：EP1434147A3
公开(公告)日：2008-01-09
申请号：EP03257664.7
申请日：2003-12-05
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Rajgopal, Suresh , Richardson, Nicholas Julian
IPC分类号： G06F17/30 , H04L12/56
CPC分类号： G06F17/30985 , G06F17/30625 , H04L45/00 , H04L45/54 , H04L45/7457 , Y10S707/922 , Y10S707/99933
摘要： Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and/or replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoded allows variable length prefix portions to be encoded.

4. 发明授权

EP1429501B1 System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine 有权
标题翻译：装置和方法用于与流水线硬件位优化算法搜索发电机路径压缩映射的多比特线索结构
公开(公告)号：EP1429501B1
公开(公告)日：2007-02-07
申请号：EP03257793.4
申请日：2003-12-11
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Richardson, Nicholas Julian , Rajgopal, Suresh
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/54 , H04L45/7457

5. 发明授权

EP1434148B1 Apparatus and method of implementing a multi-bit trie algorithmic network search engine 有权
标题翻译：设备和方法实现多bitgeordneten算法的网络搜索引擎
公开(公告)号：EP1434148B1
公开(公告)日：2013-02-20
申请号：EP03257666.2
申请日：2003-12-05
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Rajgopal, Suresh , Richardson, Nicholas Julian
IPC分类号： G06F17/30 , H04L12/54
CPC分类号： H04L45/54

6. 发明公开

EP1318450A3 Address range checking circuit and method of operation 审中-公开
标题翻译：电路用于测试地址边界和Betreibsverfahren
公开(公告)号：EP1318450A3
公开(公告)日：2004-07-07
申请号：EP02258344.7
申请日：2002-12-03
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin
IPC分类号： G06F9/34 , G06F9/355 , G06F7/02 , G06F12/08
CPC分类号： G06F9/34 , G06F7/026 , G06F12/0875 , G06F12/0891
摘要： There is disclosed an address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2 N address locations beginning at a base address location, B[M:0], wherein the address range checking circuit does not require a large comparator circuit. The address range checking circuit comprises: 1) comparison circuitry for determining if the address segment A[N-1:0] is less than the address segment B[N-1:0] and generating on a first control signal; 2) first equivalence detection circuitry for determining if the address segment A[M:N] is equal to the address segment B[M:N] and generating an A=B status signal; 3) second equivalence detection circuitry for determining if the address segment A[M:N] is equal to the address segment B[M:N] plus one and generating an A=B+1 status signal; and 4) a multiplexer that outputs the A=B status signal or the A=B+1 status signal depending on the value of the first control signal.

7. 发明公开

EP1150203A2 System and method for handling register dependency in a stack-based pipelined processor 审中-公开
标题翻译： Stapelspeicher-Pipelineprozessor在einem的Verfahren und System zur Handhabung vonRegisterabhängigkeiten
公开(公告)号：EP1150203A2
公开(公告)日：2001-10-31
申请号：EP01303827.8
申请日：2001-04-26
申请人： STMicroelectronics, Inc.
发明人： Richardson, Nicholas J. , Huang, Lun Bin
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30134 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3863
摘要： A data processor comprises a register stack comprising a plurality of architectural registers that stores operands required by instructions; an N stage instruction execution pipeline where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.
摘要翻译：数据处理器包括一个寄存器堆栈，包括存储指令所需操作数的多个架构寄存器; N级指令执行管线，其中每个处理级执行与由指令执行管线执行的待决指令相关联的多个执行步骤之一; 以及与所述N个处理级中的至少一个相关联的至少一个映射寄存器，其中所述至少一个映射寄存器存储映射数据，所述映射数据可用于确定与所述待处理指令访问的架构栈寄存器相关联的物理寄存器。

8. 发明公开

EP1434146A3 Method for increasing storage capacity in a multi-bit mapped trie-based hardware storage engine 审中-公开
标题翻译：在多bitgeordneten基于树的存储增加平均存储容量的方法，
公开(公告)号：EP1434146A3
公开(公告)日：2006-08-02
申请号：EP03257663.9
申请日：2003-12-05
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Rajgopal, Suresh , Richardson, Nicholas Julian
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06F17/30625 , Y10S707/959 , Y10S707/99933 , Y10S707/99934 , Y10S707/99942
摘要： Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.

9. 发明公开

EP1434146A2 Method for increasing storage capacity in a multi-bit mapped trie-based hardware storage engine 审中-公开
标题翻译：在多bitgeordneten基于树的存储增加平均存储容量的方法，
公开(公告)号：EP1434146A2
公开(公告)日：2004-06-30
申请号：EP03257663.9
申请日：2003-12-05
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Rajgopal, Suresh , Richardson, Nicholas Julian
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06F17/30625 , Y10S707/959 , Y10S707/99933 , Y10S707/99934 , Y10S707/99942
摘要： Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.
摘要翻译：前缀与每个单个子表包含相同长度的前缀部分由在子表中的一个或多个压缩的单个长度（CSL）的前缀的条目替换端节点的条目压缩端节点的条目终止确实含有用于前缀部分的位图端节点的条目。一种不同类型的父表索引树节点项为子表创建。其中前缀部分是非零长度的，父表中包含的位图索引端节点的条目。其中前缀部分是零长度的，父表可以任选地包含用于前缀部分的位图，作为在末端节点。的CSL节点条目内合并前缀部分的数目是基于所述前缀部分的长度。

10. 发明公开

EP1429501A1 System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine 有权
标题翻译：装置和方法用于与流水线硬件位优化算法搜索发电机路径压缩映射的多比特线索结构
公开(公告)号：EP1429501A1
公开(公告)日：2004-06-16
申请号：EP03257793.4
申请日：2003-12-11
申请人： STMicroelectronics, Inc.
发明人： Huang, Lun Bin , Richardson, Nicholas Julian , Rajgopal, Suresh
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/54 , H04L45/7457
摘要： For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.
摘要翻译：对于路由器的管道网络搜索引擎的使用，路径压缩优化的系统和方法是对游离缺失消除单次入境线索表盘。该系统嵌入在父特里结构表（1）路径压缩模式所做的数据包，（2），则跳过计数的包括公共前缀比特没有指示路径压缩模式的长度。网络搜索引擎利用的路径压缩模式和跳过计数，以消除来自数据结构单个条目字典树表。每个路径压缩模式处理的一个步幅在网络搜索引擎的后续流水线级的时间。不必要单个条目字典树表的消除减少内存空间，功耗，以及存储器访问的次数是必要的那样遍历数据结构。

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