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1. 发明公开

EP0622844A1 Method of forming low resistance contacts at the junction between regions having different conductivity types 有权转让
标题翻译：与在具有不同类型的线在区域之间的转变的低电阻接触的制造方法。
公开(公告)号：EP0622844A1
公开(公告)日：1994-11-02
申请号：EP94303007.2
申请日：1994-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis
IPC分类号： H01L21/90 , H01L21/82 , H01L21/285
CPC分类号： H01L27/11 , H01L21/28525 , H01L21/76889 , Y10S148/019
摘要： A thin film transistor structure having a first and a second polycrystalline silicon layer (36,40) of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction (42). This contact resistance is reduced by forming TiSi₂ (titanium disilicide) or other refractory metal silicides (56) such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer (40) in the P-N contact junction (42) and at the same time consumes a small portion of the underlying first polycrystalline silicon layer (36), such that the high resistance P-N junction (42) now no longer exists.
摘要翻译：具有第一和不同导电型的第二多晶硅层（36,40）（P和N）的薄膜晶体管结构具有在所得到的P-N结（42）的高电阻接触。如钴或钼中的特定区域，即P-N结的接触：该接触电阻，通过形成的TiSi2（二硅化钛）或其它难熔金属硅化物（56）减小。二硅化钛消耗在PN结接触（42）的第二多晶硅层（40）的部分，并且在所述的Sametime消耗下面的第一多晶硅层（36）没有检测高电阻PN结的一小部分（ 42）现在已经不再存在。

2. 发明公开

EP0747960A2 Memory masking for periphery salicidation of active regions 失效
标题翻译：掩蔽存储器用于外围有源区的硅化
公开(公告)号：EP0747960A2
公开(公告)日：1996-12-11
申请号：EP96303780.9
申请日：1996-05-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Nguyen, Loi Ngoc
IPC分类号： H01L27/105
CPC分类号： H01L27/105
摘要： An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

3. 发明公开

EP0547908A2 Method of forming an improved poly-buffered locos process 失效
标题翻译： Methode zur Ausbildung eines verb desserten PB-LOCOS-Verfahrens。
公开(公告)号：EP0547908A2
公开(公告)日：1993-06-23
申请号：EP92311559.6
申请日：1992-12-17
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Wei, Che-Chia , Hodges, Robert Louis , Bryant, Frank Randolph
IPC分类号： H01L21/31
CPC分类号： H01L21/32 , H01L21/76202
摘要： A method is provided for forming an improved poly-buffered LOCOS process by forming a pad oxide layer over a substrate. A first nitride layer is formed over the pad oxide layer and a polysilicon layer is formed over the first nitride layer. A second nitride layer is formed over the polysilicon layer. An opening is etched through the second nitride layer, the polysilicon layer, the first nitride layer and the pad oxide layer to expose a portion of the underlying substrate. A field oxide region is then formed in the opening.
摘要翻译：提供了一种通过在衬底上形成衬垫氧化层形成改进的多缓冲LOCOS工艺的方法。在衬垫氧化物层上形成第一氮化物层，并且在第一氮化物层上方形成多晶硅层。在多晶硅层上形成第二氮化物层。通过第二氮化物层，多晶硅层，第一氮化物层和焊盘氧化物层蚀刻开口以暴露下面的衬底的一部分。然后在开口中形成场氧化物区域。

4. 发明公开

EP0520703A1 Method for forming field oxide regions 失效
标题翻译：维尔法赫恩·赫尔斯特隆·冯·费尔德·奥格德·盖贝内恩。
公开(公告)号：EP0520703A1
公开(公告)日：1992-12-30
申请号：EP92305654.3
申请日：1992-06-19
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Liou, Fu-Tai
IPC分类号： H01L21/76
CPC分类号： H01L21/76216 , H01L21/76202
摘要： Formation of field oxide includes the formation of an opening through a nitride layer (36) to define the field oxide region (38). A conformal layer of oxide (40) is deposited over the device before a channel-stop implantation (42) is performed. The thickness and conformality of the oxide layer will affect the distance that the channel-stop implant resides from the edges of the field oxide region. During formation of field oxide, the channel-stop region will not diffuse into active regions in the substrate.
摘要翻译：场氧化物的形成包括通过氮化物层（36）形成开口以限定场氧化物区域（38）。在执行通道停止植入（42）之前，在器件上沉积保形层氧化物（40）。氧化物层的厚度和共形度将影响通道停止注入物离开场氧化物区域的边缘的距离。在场氧化物的形成期间，通道停止区域将不扩散到衬底中的有源区域中。

5. 发明公开

EP0660395A3 Self-aligned contact with zero offset to gate 失效
标题翻译：具有零自对准接触从栅极偏移。
公开(公告)号：EP0660395A3
公开(公告)日：1997-05-14
申请号：EP94308578.7
申请日：1994-11-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Nguyen, Loi , Hodges, Robert Louis
IPC分类号： H01L21/82 , H01L27/11
CPC分类号： H01L21/76897 , H01L21/768 , H01L29/6659
摘要： A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.

6. 发明公开

EP0747936A2 Method of fabricating an integrated circuit with silicided contacts 失效
标题翻译：具有触点的硅化集成电路的制备方法
公开(公告)号：EP0747936A2
公开(公告)日：1996-12-11
申请号：EP96303779.1
申请日：1996-05-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Nguyen, Loi Ngoc
IPC分类号： H01L21/285
CPC分类号： H01L21/28518
摘要： The present invention provides improved device speed by using two silicides with two different compositions: one silicide is overlaid on a polysilicon gate layer, to form a "polycide" layer with improved sheet resistance, and the other is clad on at least some "active" areas of the monocrystalline silicon, to form a "salicided" active area with improved sheet and contact resistance. Preferably one silicide is a reaction product and the other is deposited.

7. 发明公开

EP0660395A2 Self-aligned contact with zero offset to gate 失效
标题翻译： Selbstjustierender Kontakt mit Nullversatz gegen das Gate。
公开(公告)号：EP0660395A2
公开(公告)日：1995-06-28
申请号：EP94308578.7
申请日：1994-11-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Nguyen, Loi , Hodges, Robert Louis
IPC分类号： H01L21/82 , H01L27/11
CPC分类号： H01L21/76897 , H01L21/768 , H01L29/6659
摘要： A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.
摘要翻译：使用用于蚀刻停止层以及栅极上的侧壁间隔物的氮化硅（或具有低反射率和对氧化物的蚀刻选择性的另一种介电材料），用于自对准零边缘接触有源和多晶硅1的方法和结构。

8. 发明公开

EP0643419A2 Integrated circuit transistor having drain junction offset 失效
标题翻译： Integrierter Schaltungstransistor mit versetztem Drain。
公开(公告)号：EP0643419A2
公开(公告)日：1995-03-15
申请号：EP94306318.0
申请日：1994-08-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Bryant, Frank Randolph , Hodges, Robert Louis
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/78624
摘要： A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.
摘要翻译：方法包括：在导电层上形成栅极绝缘层; 添加栅电极; 形成门侧壁空间; 掩蔽漏极并将快速扩散掺杂剂（I）注入到源极区域中; 去除掩模并将慢扩散掺杂剂（II）注入到漏极区域中; 和退火以扩散掺杂剂，从而导致漏极结偏移。

9. 发明公开

EP0632492A2 Method of forming self-aligned LDD structures and low resistance contacts in thin film transistor technology devices 失效
标题翻译：形成自对准的LDD结构和低的欧姆接触的薄膜晶体管技术的安排的方法。
公开(公告)号：EP0632492A2
公开(公告)日：1995-01-04
申请号：EP94304642.5
申请日：1994-06-27
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Sundaresan, Ravishankar
IPC分类号： H01L21/336 , H01L21/283 , H01L29/786 , H01L27/11 , H01L21/8244
CPC分类号： H01L29/66765 , H01L21/76889 , H01L27/11 , H01L27/1108 , H01L29/458 , H01L29/78621
摘要： A prior art thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi 2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists.
The procedure to form low resistance contacts is extended to achieve a low leakage polysilicon TFT device. One or more LDD regions are formed to reduce the amount of leakage current of such transistor devices in an "OFF" state. The source/drain region(s) of the device are implanted with a first dopant type followed by an etch which forms spacers above the source/drain regions. Then, the source/drain regions are implanted with a second dopant type so that LDD regions are formed beneath the spacers. The electric field at the gate and source/drain boundaries of the device is spread over the entire LDD region, resulting in a lower peak electric field and hence less device leakage current.

10. 发明公开

EP0747960A3 Memory masking for periphery salicidation of active regions 失效
标题翻译： Speerehermaskierung zur Silizidierung derperiphärenaktiven Bereiche
公开(公告)号：EP0747960A3
公开(公告)日：1997-07-02
申请号：EP96303780.9
申请日：1996-05-28
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert Louis , Nguyen, Loi Ngoc
IPC分类号： H01L27/105
CPC分类号： H01L27/105
摘要： An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.
摘要翻译：集成电路存储器制造工艺和结构，其中在存储器芯片的外围（以及可选地在地线上）执行腐蚀，而不是在存储器单元的晶体管上执行。

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