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1. 发明公开

EP3353805A1 LOW PROFILE PACKAGE WITH PASSIVE DEVICE 审中-公开
公开(公告)号：EP3353805A1
公开(公告)日：2018-08-01
申请号：EP16775438.1
申请日：2016-09-22
申请人： Qualcomm Incorporated
发明人： SONG, Young Kyu , LEE, Jong-Hoon , JOW, Uei-Ming
IPC分类号： H01L23/538 , H01L25/16 , H01L21/60 , H01L25/065 , H01L23/552
CPC分类号： H01L23/552 , H01L21/4846 , H01L21/4853 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L23/5383 , H01L23/5389 , H01L24/20 , H01L25/065 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/24137 , H01L2224/24246 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/81815 , H01L2224/83005 , H01L2224/83192 , H01L2224/92225 , H01L2225/06517 , H01L2225/06537 , H01L2225/06572 , H01L2924/14 , H01L2924/1421 , H01L2924/1434 , H01L2924/15311 , H01L2924/15313 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/37001
摘要： Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) having an active face, an integrated passive device (IPD) having a face, and a redistribution layer (RDL) disposed between the IPD and the IC. The IC is embedded in a substrate. The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.

2. 发明授权

EP3140839B1 EMBEDDED PACKAGE SUBSTRATE CAPACITOR WITH CONFIGURABLE/CONTROLLABLE EQUIVALENT SERIES RESISTANCE 有权
公开(公告)号：EP3140839B1
公开(公告)日：2018-05-23
申请号：EP15719383.0
申请日：2015-04-16
申请人： Qualcomm Incorporated
发明人： SONG, Young Kyu , HWANG, Kyu-Pyung , KIM, Dong Wook , ZHANG, Xiaonan , LANE, Ryan David
IPC分类号： H01G4/30 , H01G4/33 , H01G4/40 , H01G4/224 , H01G4/236 , H01L49/02 , H05K1/16 , H01G2/10 , H05K1/18 , H05K1/02 , H05K3/46
CPC分类号： H01G4/236 , H01G2/02 , H01G2/106 , H01G4/224 , H01G4/30 , H01G4/33 , H01G4/40 , H05K1/0231 , H05K1/115 , H05K1/182 , H05K1/185 , H05K3/4644 , H05K3/4697 , H05K2201/10015 , Y10T29/42
摘要： Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

3. 发明公开

EP3308389A1 CAPACITOR STRUCTURE WITH ASYMMETRIC TERMINALS 审中-公开
标题翻译：具有不对称端子的电容器结构
公开(公告)号：EP3308389A1
公开(公告)日：2018-04-18
申请号：EP16727263.2
申请日：2016-05-18
申请人： Qualcomm Incorporated
发明人： SONG, Young Kyu , WE, Hong Bok , HWANG, Kyu-Pyung
IPC分类号： H01G4/30 , H01G4/232 , H01G2/06
CPC分类号： H01G4/228 , H01G2/065 , H01G4/012 , H01G4/12 , H01G4/232 , H01G4/30
摘要： A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

4. 发明公开

EP3108504A1 EMBEDDED MULTI-TERMINAL CAPACITOR 审中-公开
标题翻译： MEHRPOLIGER EINGEBETTETER KONDENSATOR
公开(公告)号：EP3108504A1
公开(公告)日：2016-12-28
申请号：EP15706103.7
申请日：2015-02-06
申请人： Qualcomm Incorporated
发明人： WE, Hong Bok , KIM, Dong Wook , HWANG, Kyu-Pyung , SONG, Young Kyu
IPC分类号： H01L23/498 , H01L23/50
CPC分类号： H03K3/013 , G05F3/08 , H01L23/49822 , H01L23/50 , H01L24/13 , H01L24/16 , H01L2224/13147 , H01L2224/16225 , H01L2924/13091 , H01L2924/15311 , H05K1/0306 , H05K1/183 , H05K1/184 , H05K3/306 , H05K3/4697 , H05K2201/10015 , Y10T29/49139 , H01L2924/00
摘要： An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.
摘要翻译：嵌入在衬底空腔中的嵌入式多端子电容器包括图案化成多个电源轨道和多个接地轨道的至少一个金属层。衬底包括外部电力网络。

5. 发明授权

EP3132469B1 PATTERN BETWEEN PATTERN FOR LOW PROFILE SUBSTRATE 有权
公开(公告)号：EP3132469B1
公开(公告)日：2019-01-09
申请号：EP15718725.3
申请日：2015-04-10
申请人： Qualcomm Incorporated
发明人： WE, Hong Bok , KIM, Chin-Kwan , KIM, Dong Wook , LEE, Jae Sik , HWANG, Kyu-Pyung , SONG, Young Kyu
IPC分类号： H01L23/528 , H01L21/768 , H01L23/498 , H01L23/522 , H01L21/48

6. 发明公开

EP3262681A1 INTEGRATED DEVICE PACKAGE COMPRISING CONDUCTIVE SHEET CONFIGURED AS AN INDUCTOR IN AN ENCAPSULATION LAYER 审中-公开
标题翻译：包含作为电子封装中的电感的导电片的集成器件封装
公开(公告)号：EP3262681A1
公开(公告)日：2018-01-03
申请号：EP16708334.4
申请日：2016-02-24
申请人： Qualcomm Incorporated
发明人： SONG, Young Kyu , WE, Hong Bok , HWANG, Kyu-Pyung
IPC分类号： H01L23/64 , H01F17/00 , H01F27/28 , H01F27/29 , H01F41/063 , H01L23/498
CPC分类号： H01L23/5227 , H01F27/2847 , H01F27/292 , H01F41/063 , H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L23/49822 , H01L23/5389 , H01L23/645 , H01L24/13 , H01L24/16 , H01L28/10 , H01L2224/131 , H01L2224/16227 , H01L2225/1023 , H01L2225/1041 , H01L2924/15311 , H01L2924/014
摘要： An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least one sheet of electrically conductive material configured to operate as an inductor. The sheet of electrically conductive material is at least partially encapsulated by the encapsulation layer. The sheet of electrically conductive material is configured to operate as a solenoid inductor. The sheet of electrically conductive material includes a first sheet portion, a second sheet portion coupled to the first sheet portion, where the first sheet portion and the second sheet portion form a first winding of the inductor, a first terminal portion coupled to the first sheet portion, and a second terminal portion coupled to the second sheet portion. The first sheet portion is formed on a first level of the sheet. The second sheet portion is formed on a second level of the sheet.

7. 发明公开

EP3198641A1 SEMICONDUCTOR PACKAGE INTERCONNECTIONS AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：半导体封装互连及其制造方法
公开(公告)号：EP3198641A1
公开(公告)日：2017-08-02
申请号：EP15775578.6
申请日：2015-09-25
申请人： Qualcomm Incorporated
发明人： KIM, Dong Wook , LEE, Jae Sik , WE, Hong Bok , SONG, Young Kyu , KIM, Chin-Kwan , HWANG, Kyu-Pyung , GU, Shiqun
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L23/49811 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/92 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/81203 , H01L2224/81815 , H01L2224/8203 , H01L2224/92124 , H01L2224/92125 , H01L2224/92244 , H01L2225/1035 , H01L2924/1431 , H01L2924/1434 , H01L2924/00
摘要： A semiconductor package according to some examples of the disclosure may include a base (110) with a first redistribution layer (150) on one side, first (120) and second (130) side-by-side die attached to the base on an opposite side from the first redistribution layer, an interposer (140) attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias (180,181) extending from the first and second die to a second redistribution layer (170) on a surface of the package opposite the first redistribution layer, and a plurality of package vias (182) extending through the package between the first and second redistribution layers.
摘要翻译：根据本公开的一些示例的半导体封装件可以包括基底，在一侧具有第一再分布层，在与第一再分布层相对的一侧上附着到基底的第一和第二并排管芯，附着到有源侧的插入物提供第一和第二管芯之间的互连;多个管芯通孔，从第一和第二管芯延伸到与第一再分配层相对的封装表面上的第二再分配层;以及多个在第一和第二重新分布层之间延伸穿过封装的封装过孔。

8. 发明公开

EP3164888A1 HIGH QUALITY FACTOR FILTER IMPLEMENTED IN WAFER LEVEL PACKAGING (WLP) INTEGRATED DEVICE 审中-公开
标题翻译：在晶圆级封装（WLP）集成器件中实现的高品质因数滤波器
公开(公告)号：EP3164888A1
公开(公告)日：2017-05-10
申请号：EP15738228.4
申请日：2015-07-01
申请人： Qualcomm Incorporated
发明人： LEE, Jong-Hoon , SONG, Young Kyu , YOON, Jung Ho , JOW, Uei Ming , ZHANG, Xiaonan , LANE, Ryan David
IPC分类号： H01L23/64 , H01L23/522 , H05K1/16 , H01F17/00
CPC分类号： H01L23/645 , H01F17/0013 , H01F2017/0086 , H01L23/3128 , H01L23/5223 , H01L23/5227 , H01L23/525 , H01L2224/0401 , H01L2224/05008 , H01L2224/05147 , H01L2224/05569 , H01L2224/05572 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2225/1023 , H01L2225/1058 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30107 , H05K1/111 , H05K1/165 , H05K2201/10674 , H01L2924/014
摘要： Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.
摘要翻译：一些实现提供了包括电容器和电感器的集成器件。电感器电耦合到电容器。电感器和电容器被配置为用作集成器件中的电信号的滤波器。电感器包括印刷电路板（PCB）的第一金属层，耦合到PCB的一组焊球以及模具中的第二金属层。在一些实现中，电容器位于管芯中。在一些实现中，电容器是PCB上的表面安装无源器件。在一些实施方式中，第一金属层是PCB上的迹线。在一些实施方式中，电感器包括管芯中的第三金属层。在一些实施方式中，第二金属层是裸片的凸块下金属化（UBM）层，并且第三金属是裸片的再分布层。

9. 发明公开

EP3069356A1 SOLONOID INDUCTOR IN A SUBSTRATE 有权
标题翻译：基片中的SOLONOID电感
公开(公告)号：EP3069356A1
公开(公告)日：2016-09-21
申请号：EP14802565.3
申请日：2014-11-06
申请人： Qualcomm Incorporated
发明人： KIM, Daeik Daniel , SONG, Young Kyu , ZHANG, Xiaonan , KIM, Jonghae
IPC分类号： H01F17/00 , H01F41/04
摘要： Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.
摘要翻译：一些实现提供了在衬底中包括衬底和电感器的集成器件（例如，半导体器件）。在一些实施方式中，电感器是螺线管电感器。电感器包括一组绕组。该组绕组具有内部周边。该组绕组包括一组互连和一组过孔。该组互连和该组过孔位于该组绕组的内周边之外。在一些实施方式中，该组绕组还包括一组捕捉垫。该组互连线通过该组捕捉垫耦合到该组通孔。在一些实施方式中，该组绕组具有外周。该组焊盘联接到该组互连，使得该组焊盘至少部分地位于该组绕组的外周边之外。

10. 发明公开

EP3311389A1 INDUCTOR STRUCTURE IN A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件中的电感结构
公开(公告)号：EP3311389A1
公开(公告)日：2018-04-25
申请号：EP16730638.0
申请日：2016-06-06
申请人： Qualcomm Incorporated
发明人： JOW, Uei-Ming , SONG, Young Kyu , LEE, Jong-Hoon , YOON, Jung Ho , CHOI, Sangjo , ZHANG, Xiaonan
IPC分类号： H01F17/00 , H01F41/04
摘要： An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

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