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1. 发明授权

EP3433728B1 PROVIDING REFERENCES TO PREVIOUSLY DECODED INSTRUCTIONS OF RECENTLY-PROVIDED INSTRUCTIONS TO BE EXECUTED BY A PROCESSOR 有权
公开(公告)号：EP3433728B1
公开(公告)日：2020-01-01
申请号：EP17711492.3
申请日：2017-03-03
申请人： Qualcomm Incorporated
发明人： KOTHINTI NARESH, Vignyan Reddy , PRIYADARSHI, Shivam , DAMODARAN, Raguram
IPC分类号： G06F9/38

2. 发明公开

EP3433728A1 PROVIDING REFERENCES TO PREVIOUSLY DECODED INSTRUCTIONS OF RECENTLY-PROVIDED INSTRUCTIONS TO BE EXECUTED BY A PROCESSOR 审中-公开
公开(公告)号：EP3433728A1
公开(公告)日：2019-01-30
申请号：EP17711492.3
申请日：2017-03-03
申请人： Qualcomm Incorporated
发明人： KOTHINTI NARESH, Vignyan Reddy , PRIYADARSHI, Shivam , DAMODARAN, Raguram
IPC分类号： G06F9/38
摘要： Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor is disclosed herein. In one aspect, a low resource micro-operation controller is provided. Responsive to an instruction pipeline receiving an instruction address, the low resource micro-operation controller is configured to determine if the received instruction address corresponds to an instruction address in short history table. Short history table includes instruction addresses of recently-provided instructions having micro-ops in a post-decode queue. If the received instruction address corresponds to an instruction address in short history table, the low resource micro-operation controller is configured to provide reference (e.g., pointer) to the fetch stage that corresponds to an entry in the post-decode queue in which the micro-ops corresponding to the instruction address are stored. Responsive to the decode stage receiving the reference, the low resource micro-operation controller is configured to provide the micro-ops from the post-decode queue for execution.

3. 发明授权

EP3423937B1 DYNAMIC PIPELINE THROTTLING USING CONFIDENCE-BASED WEIGHTING OF IN-FLIGHT BRANCH INSTRUCTIONS 失效
公开(公告)号：EP3423937B1
公开(公告)日：2020-04-22
申请号：EP17707718.7
申请日：2017-02-06
申请人： Qualcomm Incorporated
发明人： PRIYADARSHI, Shivam , AL SHEIKH, Rami Mohammad , DAMODARAN, Raguram , MCILVAINE, Michael Scott , BRIDGES, Jeffrey Todd
IPC分类号： G06F9/38

4. 发明公开

EP3353662A1 METHOD AND APPARATUS FOR CACHE LINE DEDUPLICATION VIA DATA MATCHING 审中-公开
公开(公告)号：EP3353662A1
公开(公告)日：2018-08-01
申请号：EP16766817.7
申请日：2016-09-12
申请人： Qualcomm Incorporated
发明人： CAIN III, Harold Wade , HOWER, Derek Robert , DAMODARAN, Raguram , SARTORIUS, Thomas Andrew
IPC分类号： G06F12/0842 , G06F12/0895 , G06F12/0815 , G06F12/0888
CPC分类号： G06F12/121 , G06F12/0808 , G06F12/0815 , G06F12/0842 , G06F12/0888 , G06F12/0895 , G06F12/12 , G06F2212/1044 , G06F2212/621 , Y02D10/13
摘要： A cache fill line is received, including an index, a thread identifier, and cache fill line data. The cache is probed, using the index and a different thread identifier, for a potential duplicate cache line. The potential duplicate cache line includes cache line data and the different thread identifier. Upon the cache fill line data matching the cache line data, duplication is identified. The potential duplicate cache line is set as a shared resident cache line, and the thread share permission tag is set to a permission state.

5. 发明公开

EP3423937A1 DYNAMIC PIPELINE THROTTLING USING CONFIDENCE-BASED WEIGHTING OF IN-FLIGHT BRANCH INSTRUCTIONS 失效
公开(公告)号：EP3423937A1
公开(公告)日：2019-01-09
申请号：EP17707718.7
申请日：2017-02-06
申请人： Qualcomm Incorporated
发明人： PRIYADARSHI, Shivam , AL SHEIKH, Rami Mohammad , DAMODARAN, Raguram , MCILVAINE, Michael Scott , BRIDGES, Jeffrey Todd
IPC分类号： G06F9/38
摘要： Systems and methods for operating a processor include determining confidence levels, such as high, low, and medium confidence levels, associated with in-flight branch instructions in an instruction pipeline of the processor, based on counters used for predicting directions of the in-flight branch instructions. Numbers of in-flight branch instructions associated with each of confidence levels are determined. A weighted sum of the numbers weighted with weights corresponding to the confidence levels is calculated and the weighted sum is compared with a threshold. A throttling signal may be asserted to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.

6. 发明公开

EP3335112A1 STORING NARROW PRODUCED VALUES FOR INSTRUCTION OPERANDS DIRECTLY IN A REGISTER MAP IN AN OUT-OF-ORDER PROCESSOR 审中-公开
公开(公告)号：EP3335112A1
公开(公告)日：2018-06-20
申请号：EP16745935.3
申请日：2016-07-14
申请人： Qualcomm Incorporated
发明人： KRISHNA, Anil , SMITH, Rodney Wayne , NAVADA, Sandeep Suresh , PRIYADARSHI, Shivam , DAMODARAN, Raguram
IPC分类号： G06F9/38
CPC分类号： G06F9/3005 , G06F9/30098 , G06F9/30112 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor (OoP) is provided. An OoP is provided that includes an instruction processing system. The instruction processing system includes a number of instruction processing stages configured to pipeline the processing and execution of instructions according to a dataflow execution. The instruction processing system also includes a register map table (RMT) configured to store address pointers mapping logical registers to physical registers in a physical register file (PRF) for storing produced data for use by consumer instructions without overwriting logical registers for later executed, out-of-order instructions. In certain aspects, the instruction processing system is configured to write back (i.e., store) narrow values produced by executed instructions directly into the RMT, as opposed to writing the narrow produced values into the PRF in a write back stage.

7. 发明公开

EP3436930A1 PROVIDING LOAD ADDRESS PREDICTIONS USING ADDRESS PREDICTION TABLES BASED ON LOAD PATH HISTORY IN PROCESSOR-BASED SYSTEMS 有权
公开(公告)号：EP3436930A1
公开(公告)日：2019-02-06
申请号：EP17711898.1
申请日：2017-03-02
申请人： Qualcomm Incorporated
发明人： AL SHEIKH, Rami, Mohammad , DAMODARAN, Raguram
IPC分类号： G06F9/38

8. 发明公开

EP3353625A1 METHOD AND APPARATUS FOR EFFECTIVE CLOCK SCALING AT EXPOSED CACHE STALLS 审中-公开
公开(公告)号：EP3353625A1
公开(公告)日：2018-08-01
申请号：EP16770809.8
申请日：2016-08-25
申请人： Qualcomm Incorporated
发明人： PRIYADARSHI, Shivam , KRISHNA, Anil , DAMODARAN, Raguram , BRIDGES, Jeffrey Todd , SPEIER, Thomas Philip , SMITH, Rodney Wayne , BOWMAN, Keith Alan , HANSQUINE, David Joseph Winston
IPC分类号： G06F1/32 , G06F9/38
CPC分类号： G06F1/08 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F12/0804 , G06F12/0875 , G06F12/0897 , G06F12/12 , G06F2212/1024 , G06F2212/60 , Y02D10/126 , Y02D10/152
摘要： The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

9. 发明公开

EP3335110A1 POWER EFFICIENT FETCH ADAPTATION 审中-公开
公开(公告)号：EP3335110A1
公开(公告)日：2018-06-20
申请号：EP16739672.0
申请日：2016-07-11
申请人： Qualcomm Incorporated
发明人： PRIYADARSHI, Shivam , AL SHEIKH, Rami Mohammad , DAMODARAN, Raguram
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3802 , G06F9/3844 , G06F12/0875 , G06F2212/452
摘要： Systems and methods relate to an instruction fetch unit of a processor, such as a superscalar processor. The instruction fetch unit includes a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a fetch group of instructions in a pipeline stage of the processor. A first entry of the FBWP corresponding to the fetch group corresponds to a prediction of the number of instructions to be fetched, based on occurrence and location of a predicted taken branch instruction in the fetch group and a confidence level associated with the predicted number in the prediction field. The instruction fetch unit is configured to fetch only the predicted number of instructions, rather than the maximum number of entries that can be fetched in the pipeline stage, if the confidence level is greater than a predetermined threshold. In this manner, wasteful fetching of instructions is avoided.

10. 发明公开

EP3123305A1 SPECULATIVE HISTORY FORWARDING IN OVERRIDING BRANCH PREDICTORS, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：投机发展前进中的VERZWEIGUNGSPRÄDIKATOREN及相关电路，方法和计算机可读介质取消
公开(公告)号：EP3123305A1
公开(公告)日：2017-02-01
申请号：EP15716237.1
申请日：2015-03-23
申请人： Qualcomm Incorporated
发明人： AL SHEIKH, Rami, Mohammad , DAMODARAN, Raguram
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3844
摘要： Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media are disclosed. In one embodiment, a branch prediction circuit including a first branch predictor and a second branch predictor is provided. The first branch predictor generates a first branch prediction for a conditional branch instruction, and the first branch prediction is stored in a first branch prediction history. The first branch prediction is also speculatively forwarded to a second branch prediction history. The second branch predictor subsequently generates a second branch prediction based on the second branch prediction history, including the speculatively forwarded first branch prediction. By enabling the second branch predictor to base its branch prediction on the speculatively forwarded first branch prediction, an accuracy of the second branch predictor may be improved.
摘要翻译：投机历史转发在压倒一切的分支预测，以及相关的电路，方法和计算机可读介质游离缺失盘。在一个，分支预测电路实施方式，包括第一分支预测器和一个第二分支预测器被设置。第一分支预测基因汇率在一个条件转移指令第一分支预测，与第一分支预测存储在第一分支预测历史。因此，第一分支预测推测性地转发至第二分支预测历史。第二分支预测随后基因费率基于第二分支预测历史第二分支预测，包括推测性地转送第一分支预测。通过使所述第二分支预测器到基座上的第二分支预测准确度的推测性地转送第一分支预测其分支预测可以得到改善。

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