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1. 发明授权

EP0397268B1 Integrated circuit comprising a signal level converter 失效
标题翻译：具有信号电平变换的集成电路。
公开(公告)号：EP0397268B1
公开(公告)日：1995-11-29
申请号：EP90201161.8
申请日：1990-05-07
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , Dikken, Jan , Schuhmacher, Hans-Jürgen Otto
IPC分类号： H03K19/003 , H03K19/017 , H03K17/04
CPC分类号： H03K19/00384 , H03K19/01707

2. 发明授权

EP0400724B1 Integrated memory comprising a sense amplifier 失效
标题翻译：一种集成电路存储器用的读出放大器。
公开(公告)号：EP0400724B1
公开(公告)日：1995-08-23
申请号：EP90201307.7
申请日：1990-05-23
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419

3. 发明授权

EP0400728B1 Integrated memory comprising a sense amplifier 失效
标题翻译：一种集成电路存储器用的读出放大器。
公开(公告)号：EP0400728B1
公开(公告)日：1995-08-02
申请号：EP90201314.3
申请日：1990-05-25
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/065 , G11C11/419

4. 发明公开

EP0380152A1 Transistor circuit 失效
标题翻译： Transistorschaltung。
公开(公告)号：EP0380152A1
公开(公告)日：1990-08-01
申请号：EP90200067.8
申请日：1990-01-11
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , Dikken, Jan , Schumacher, Hans-Jürgen Otto
IPC分类号： H03F3/45 , H03K5/02
CPC分类号： H03K19/00361 , H03F1/3211 , H03F3/4565 , H03F3/45654 , H03F3/45659 , H03F2203/45394 , H03K19/018521
摘要： A transistor circuit (1), comprising a first differential amplifier (N₁, N₂) which is composed of a differential pair (N₁, N₂) and a current mirror (P₂, P₃). The transistor circuit in accordance with the invention comprises a second differential amplifier (10) which measures a differential offset voltage and reduces this offset voltage by means of common mode current feedback. The transistor circuit thus offers a stable amplifier having a high speed and a low offset voltage. Such a transistor circuit can be advantageously used in a logic output buffer so that, for example an ECL output buffer can be realized in CMOS.
摘要翻译：一种晶体管电路（1），包括由差分对（N1，N2）和电流镜（P2，P3）组成的第一差分放大器（N1，N2）。根据本发明的晶体管电路包括测量差分偏移电压并通过共模电流反馈减小该偏移电压的第二差分放大器（10）。因此，晶体管电路提供了具有高速度和低失调电压的稳定放大器。这样的晶体管电路可以有利地用在逻辑输出缓冲器中，使得例如ECL输出缓冲器可以在CMOS中实现。

5. 发明授权

EP0155039B1 Current-source arrangement 失效
标题翻译：电流安排
公开(公告)号：EP0155039B1
公开(公告)日：1989-10-18
申请号：EP85200254.2
申请日：1985-02-25
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , van Tuijl, Adrianus Johannes Maria
IPC分类号： G05F3/22
CPC分类号： G05F3/227

6. 发明公开

EP0309063A1 Amplifier arrangement 失效
标题翻译：放大器排列
公开(公告)号：EP0309063A1
公开(公告)日：1989-03-29
申请号：EP88202067.0
申请日：1988-09-22
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , de Jager, Willem , Buitendijk, Pieter
IPC分类号： H03F3/30 , H03F1/32
CPC分类号： H03F3/3093 , H03F1/3217 , H03F2203/30045
摘要： The first (T₁) and the second (T₂) output transistor of an amplifier arrangement are push-pull driven by means of a drive circuit (10) having two transistors (T₁₁, T₁₂) which are each loaded by a current source (T₁₃, T₁₄). Currents which are a measure of the currents flowing through the first (T₁) and the second (T₂) output transistor are generated by a first (20) and second (30) current measuring means. These currents are applied to a negative feedback means (40) which controls the current intensity of the current sources (T₁₃, T₁₄) in such a way that the harmonic mean value of the currents flowing through the first (T₁) and the second (T₂) output transistor is substantially equal to a reference value.
摘要翻译：放大器装置的第一（T 1）和第二（T 2）输出晶体管通过具有两个晶体管（T 11，T 12）的驱动电路（10）进行推挽驱动，每个晶体管由电流源（T 13， T₁₄）。用第一（20）和第二（30）电流测量装置产生流过第一（T 1）和第二（T 2）输出晶体管的电流的量度的电流。这些电流加到负反馈装置（40），该装置控制电流源（T 13，T 14）的电流强度，使得流过第一（T 1）和第二（T 2）电流的谐波平均值）输出晶体管基本上等于参考值。

7. 发明公开

EP0173370A1 Amplifier arrangement 失效
标题翻译： Verstärkereinrichtung。
公开(公告)号：EP0173370A1
公开(公告)日：1986-03-05
申请号：EP85201180.8
申请日：1985-07-12
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , Wassenaar, Roelof Foppe
IPC分类号： H03F1/02 , H03F3/45
CPC分类号： H03F3/45183 , H03F1/0261 , H03F2203/45364 , H03F2203/45466 , H03F2203/45674
摘要： 57 A bias current (I t ) which is dependent on the input signal (V i ) is applied to the junction point (2) of the source electrodes of a first and a second transistor (T 1 , T 2 ). The amplifier comprises a control circuit, which ensures that this bias current (l t ) cannot increase more than is necessary to obtain a high slew rate, thereby minimizing dissipation by the arrangement. This control circuit comprises a third and a fourth transistor (T 3 , T 4 ) which are arranged in parallel with the first transistor (T,) and the second transistor (T 2 ), respectively, and which carry currents (l 3 ,l 4 ) which are proportional to the currents (l 1 , l 2 ) in the first and the second transistor (T,, T 2 ). A selection circuit (5) applies the smaller of the two currents (I 3 , 1 4 ) in the third and the fourth transistor (T 3 , T 4 ) to an output (8), where this current is compared with a reference current (I 0 ) from a current source (9). The difference between these currents is applied to a current amplifier (10), which supplies an increasing bias current (l t ) until the smaller of the two currents (1 3 , 1 4 ) in the third and the fourth transistor (T 3 , T 4 ) has become equal to the reference current (l o ).
摘要翻译：依赖于输入信号（Vi）的偏置电流（It）被施加到第一和第二晶体管（T1，T2）的源极的接合点（2）。该放大器包括控制电路，其确保该偏置电流（It）不能比获得高压摆率所需的增加更多，从而通过该布置最小化耗散。该控制电路包括分别与第一晶体管（T1）和第二晶体管（T2）并联布置的第三和第四晶体管（T3，T4），并且具有与第一和第二晶体管（T1，T2）中的电流（I1，I2）。选择电路（5）将第三和第四晶体管（T3，T4）中的两个电流（I3，I4）中的较小的一个电路施加到输出（8），其中该电流与基准电流（I0）电流源（9）。这些电流之间的差异被施加到电流放大器（10），其提供增加的偏置电流（It），直到第三和第四晶体管（T3，T4）中的两个电流（I3，I4）中的较小的一个等于参考电流（I0）。

8. 发明授权

EP0454250B1 Reference generator 失效
标题翻译：基准信号发生器
公开(公告)号：EP0454250B1
公开(公告)日：1995-12-20
申请号：EP91200953.7
申请日：1991-04-22
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , Costello, Philip David
IPC分类号： G05F3/26
CPC分类号： G05F3/262 , Y10S323/907

9. 发明公开

EP0400724A1 Integrated memory comprising a sense amplifier 失效
标题翻译：集成存储器包括一个读出放大器
公开(公告)号：EP0400724A1
公开(公告)日：1990-12-05
申请号：EP90201307.7
申请日：1990-05-23
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419
摘要： An integrated memory comprising a sense amplifier which includes a parallel connection of a first and a second current branch, each current branch including channels of a control transistor and a load transistor which are coupled via a relevant junction point, the relevant junction points on the one side and gates of the load transistors on the other side being cross-wise coupled, said junction points constituting outputs of the sense amplifier, said transistors being of the same conductivity type, each load transistor being connected in a source-follower configuration with the relevant control transistor. As a result, the control transistors will be operative in the saturation region at all times and can be driven to full output, so that an integrated memory in accordance with the invention is faster.
摘要翻译：一种包括读出放大器的集成存储器，所述读出放大器包括第一和第二电流分支的并联连接，每个电流分支包括控制晶体管和负载晶体管的沟道，所述控制晶体管和负载晶体管的沟道经由相关联结点耦合，所述一个所述负载晶体管的另一侧的栅极和栅极交叉耦合，所述接点构成读出放大器的输出，所述晶体管具有相同的导电类型，每个负载晶体管以源极跟随器配置与相关控制晶体管。结果，控制晶体管将始终在饱和区工作并且可以被驱动为全输出，从而根据本发明的集成存储器更快。

10. 发明公开

EP0397268A1 Integrated circuit comprising a signal level converter 失效
标题翻译： Integrierte Schaltung mit einem Signalpegelumsetzer。
公开(公告)号：EP0397268A1
公开(公告)日：1990-11-14
申请号：EP90201161.8
申请日：1990-05-07
申请人： Philips Electronics N.V.
发明人： Seevinck, Evert , Dikken, Jan , Schuhmacher, Hans-Jürgen Otto
IPC分类号： H03K19/003 , H03K19/017 , H03K17/04
CPC分类号： H03K19/00384 , H03K19/01707
摘要： An integrated circuit comprises a converter for converting a logic input signal of a first logic type into a logic output signal of a second logic type, for example from ECL to CMOS level. The converter comprises a buffer (10), including a controllable load (14) and a driver transistor (12), and a control circuit (20). In dependence on a control voltage and a reference voltage (V REF ) externally applied, the load (14) is controlled so that the output signal (V OUT ) is substantially equal to the reference voltage (V REF ) if the input signal (V IN ) is substantially equal to the control voltage. The load (14) and the driver transistor (12) in the buffer are controllable in a mutually opposed manner, a capacitance (25) being inserted between the control terminal of the load and the input terminal (16) of the driver so as to pass the AC effect of signal transitions to the load, thus speeding up the transition at the buffer. In one embodiment the control circuit (20) comprises a copy (30) of the buffer (10), which copy (30) receives the control voltage on its input, its load being controlled by a differential amplifier (40) whose inputs receive the reference voltage (V REF ) and the output voltage of the copy. A CMOS-SRAM comprising ECL/CMOS level converters of the above kind communicates with fast ECL circuits and has a low energy consumption.
摘要翻译：集成电路包括转换器，用于将第一逻辑类型的逻辑输入信号转换为第二逻辑类型的逻辑输出信号，例如从ECL到CMOS电平。该转换器包括一个包括可控负载（14）和一个驱动晶体管（12）的缓冲器（10）和一个控制电路（20）。根据外部施加的控制电压和参考电压（VREF），如果输入信号（VIN）基本上等于负载（14），则输出信号（VOUT）基本上等于参考电压（VREF）等于控制电压。缓冲器中的负载（14）和驱动晶体管（12）以相互相对的方式可控，电容（25）插入在负载的控制端和驱动器的输入端（16）之间，以便将信号转换的交流效应传递给负载，从而加快缓冲器的转换。在一个实施例中，控制电路（20）包括缓冲器（10）的副本（30），其复制（30）在其输入端接收控制电压，其负载由差分放大器（40）控制，差分放大器（40）的输入接收参考电压（VREF）和复印的输出电压。包括上述类型的ECL / CMOS电平转换器的CMOS-SRAM与快速ECL电路通信并且具有低能量消耗。

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